George E. Konstantoulakis

Efficient modeling of VBR MPEG-1 coded video sources

The performance evaluation of broadband networks requires statistical analysis and modeling of the actual network traffic. Since multimedia services, and especially variable bit rate (VBR) MPEG-coded video streams are expected to be a major traffic component carried by these networks, modeling of such services and accurate estimation of network resources are crucial for proper network design and congestion-control mechanisms that can guarantee the negotiated quality of service at a minimum cost. The layer modeling of MPEG-1 coded video streams and statistical analysis of their traffic characteristics at each layer is proposed, along with traffic models capable of estimating the network resources over asynchronous transfer mode (ATM) links. First, based on the properties of the entire MPEG-1 sequence (frame layer signal), a model (Model A) is presented by correlating three stochastic processes in discrete time (autoregressive models), each of which corresponds to the three types of frames of the MPEG encoder (I, P, and B frames). To simplify the traffic Model A and to reduce the required number of parameters, we study the MPEG stream at a higher layer by considering a signal, which expresses the average properties of I, P, and B frames over a group of picture (GOP) period. However, models on this layer cannot accurately estimate the network resources, especially in multiplexing schemes. For this reason, an intermediate layer is introduced, which exploits and efficiently combines information of both the aforementioned layers, producing a model (Model B), which requires much smaller number of parameters than Model A and simultaneously provides satisfactory results as far as the network resources are concerned. Evaluation of the validity of the proposed models is performed through experimental studies and computer simulations, using several long duration VBR MPEG-1 coded sequences, different from that used in modeling. The results indicate that both Models A and B are good estimators of video traffic behavior over ATM links at a wide range of utilization.

Processing and scheduling components in an innovative network processor architecture

In this paper, we describe the architecture of an innovative network processor aiming at the acceleration of packet processing in high speed network interfaces and at the tight coupling of low and high level protocols. The proposed design uses programmable hard-wired components with line rate throughput and is capable of executing protocols and handling efficiently high and low level streaming operations. We discuss the details of the main innovation of the proposed design, which incorporates a three stage RISC-based pipelined module and a composite scheduling unit for internal resource management and outgoing traffic shaping. When both components are integrated on the same platform then maximum and fair utilization of the available resources is achieved. Quantitative performance results are given, both by means of microcode profiling and simulation for indicative applications of the protocol processor.

Design and performance evaluation of a Programmable Packet Processing Engine (PPE) suitable for high-speed network processors units

In this paper, we present a Programmable Packet Processing Engine suitable for deep header processing in high-speed networking systems. The engine, which has been - fabricated as part of a complete network processor, consists of a typical RISC-CPU, whose register file has been modified in order to support efficient context switching, and two simple special-purpose processing units. The engine can be used in a number of network processing units (NPUs), as an alternative to the typical design practice of employing a large number of simple general purpose processors, or in any other embedded system designed to process mainly network protocols. To assess the performance of the engine, we have profiled typical networking applications and a series of experiments were carried out. Further, we have compared the performance of our processing engine to that of two widely used NPUs and show that our proposed packet-processing engine can run specific applications up to three times faster. Moreover, the engine is simpler to be fabricated, less complex in terms of hardware complexity, while it can still be very easily programmed.

Performance models for multiplexed VBR MPEG video sources

This paper performs issues relative to modeling of VBR MPEG coded video sources over ATM B-ISDN networks. Firstly, we analyse the statistical characteristics of the three types of frames, which the MPEG algorithm generates, and we study their autocovariance and probability density functions. Based on the data analysis, we propose two new source models which approximate both the statistical properties and the traffic characterization of MPEG sequences. The second source model (model B) has been introduced in order to reduce significantly the number of parameters which are necessary for our modeling. To verify the good fitness of the proposed new models, a statistical multiplexing configuration over ATM B-ISDN networks has been implemented and cell as well as frame loss probability have been estimated when the bit stream of video sources is generated by the real data and the two proposed models.

Hardware Architectures for the Efficient Implementation of Multi-Service Broadband Access and Multimedia Home Networks

In multimedia applications, the stringent requirements for balancing transmission capacity, flexible service provisioning and cost reduction lead the manufactures to provide highly integrated System-on Chip (SoC) solutions. This paper analyzes the application of high-bandwidth-networking SoCs to improve on the cost efficiency of multimedia service distribution in home networks. We present a case study, where we utilize the inherent protocol processing capabilities and high bandwidth interfaces of a modern network processor, scaled down to match the performance targets and low cost requirements of the home networking environment. An efficient, low cost Residential Gateway architecture results by mapping the home services onto the processing and memory blocks of this SoC.

Transfer of data over ATM networks using available bit rate (ABR)

The paper contributes to currently debated key issues on the evolution of ATM networks and their standardisation. It takes the view that since the asynchronous transfer mode has features of both circuit and packet switching, one has to selectively draw benefits for different types of traffic, compromising, if necessary, the integration principle. The use of the available bit rate (ABR), promoted by the ATM Forum for handling time insensitive (best effort) traffic, is fully adopted and its influence on switching discussed in detail. Coupled with ABR for transmission, the paper supports the employment of massive memory within the switching equipment. By suggesting solutions to key memory management problems, it also examines the use of X.25-like flow and congestion control, selectively employed for data transfer over ATM networks.

An innovative scheduling scheme for high-speed network processors

In this paper, we describe the architecture of the scheduling components integrated in a novel programmable processor architecture. The paper explores the requirements for scheduling in the environment of a network processor, designed for efficient protocol processing in high-speed networking. We focus on the implementation of services with weighted priorities and shaping of traffic on the transmission path as a means to support QoS for real time applications. Taking into account that one of the main problems when designing hardware devices for network processing is the relatively low throughput and capacity of the memories (mainly off-chip) we describe design alternatives and analyze the performance vs. cost trade-offs. The architecture of a novel processor architecture developed by the Protocol Processor Project (PRO3) is described and is used as reference to explore the intricacies of the scheduler components and identify parameters that affect the components design and performance.

Traffic characterisation and modelling of VBR coded MPEG sources

This paper intends to study the characteristics of VBR MPEG sources and performs models for their traffic behaviour. Our analysis focuses on long-time MPEG video films, approximately 27 min. Known probability density functions (pdf) are presented which fit well with real the pdf of I, P, B and Group of pictures (GOP) frames. In order to approximate the traffic behaviour, we study the autocovariance factions of the previous frames and we propose two different models so as to achieve the necessary fit. The first model is based on GOP frame layer which is able to approximate the cell probability loss at utilisation about 0.7-0.85 but it slightly overestimates the frame loss probability. The other model correlates the error of I, P and B AR models without spoiling the i.i.d. (independent identical distributed) property. Our results show that the latter model approximates well the cell as well as the frame loss probabilities.

Efficient field processing cores in an innovative protocol processor system-on-chip

We present an innovative protocol processor component that combines wire-speed processing for low-level, and best effort processing for higher-level protocols. The component is a System-on-Chip that integrates variable size packet buffering, specialised cores for header and field processing, generic RISC cores and scheduling blocks. We focus on the main innovation, the reprogrammable pipeline module, and discuss its internal architecture, optimised to perform field processing on byte streams, as well as protocol processing on complex data structures. Furthermore, we present how modern and new tools were used in system dimensioning, design, and verification phases. The chip is able to handle up to 512K flows organised in individual queues. It embeds 5 custom cores optimised for field processing, 3 typical RISC cores for packet processing and 11 generic and application specific hardware blocks. Itýs been prototyped in UMC 0.18uCMOS technology in a 1096-pin BGA package and operates at 200MHz for 2.5Gbps links.

A Parallel VLSI Video/Communication Controller

This paper presents a VLSI architecture specifically designed as a video/communication controller to support emerging applications in the area of video/data communications. The controller is a parallel architecture consisting of three (3) processing modules, a shared memory with four (4) banks and two (2) input/output modules and operating at the transfer speed of 622 Mbits/sec. The processing modules and memory banks communicate through a low cost interconnection scheme able though to perform at systems required data transfer rate. The entire system constitutes a component which can accommodate a switching system as an intelligent buffer with real time processing and multiplexing capabilities. The component performs operations on fixed and/or variable length packets of data on a stream basis. The architecture embeds both the processing and the memory modules, thus producing a “system on a chip” solution.