George J. Milne

The formal description and verification of hardware timing

A formalism in which timing properties of digital hardware may be specified, derived, and formally verified is introduced as a rigorous theory for hardware timing. A rigorous modeling framework has been used to create a family of related verification techniques rather than a single timing analysis tool. This framework is based on a model of interacting finite state machines called CIRCAL, a formalism developed for the purpose of describing and validating complex concurrent systems. In this approach to hardware timing analysis, the presence of a composition operator is all-pervasive. It provides a single, uniform mechanism for describing the behavior of interacting hardware modules and for establishing and describing the timing properties of such modules. >

Realising massively concurrent systems on the SPACE machine

Highly concurrent systems occur frequently in the physical world. This paper focuses on a class of systems characterised as being highly concurrent and which are composed out of many simple parts which interact with other parts in their locality. It discusses how to describe these systems and introduces a cellular automata type of architecture which is used to simulate these systems directly in hardware, with physical concurrency being realised by true hardware concurrency. The architecture of the SPACE machine (Scalable Parallel Architecture for Concurrency Experiments), which is constructed from reconfigurable FPGA logic, is introduced and it is demonstrated how to simulate road traffic systems using it.<<ETX>>

Design for verifiability

The concept of Design for Verifiability is introduced as a means of attacking the complexity problem encountered when verifying the correctness of hardware designs using mathematical proof techniques. The inherent complexity of systems implemented as integrated circuits results in a comparable descriptive complexity when modelling them in any framework which supports formal verification. Performing formal verification then rapidly becomes intractable as a consequence of this descriptive complexity. In this paper we propose a strategy for dealing, at least in part, with this problem. We advocate the use of a particular design strategy involving the use of structural design rules which constrain the behaviour of a design resulting in a less complex design verification. The term Design for Verifiability is used to capture this concept in an analogous way to the term Design for Testability.

A Highly Parallel FPL-Based Machine and Its Formal Verification

The SPACE machine is introduced as a new type of computer architecture, capable of very fast simulation of highly concurrent systems. The machine is designed to be scalable, constructed from a vast array of boards. The decisions made in the the design of the board are discussed, and the actual hardware (based on an array of Field Programmable Gate Array chips) is described. It is shown that this machine can be programmed by translating a subset of the Occam language into asynchronous modules. Using the Circal process algebra, a new method of formally verifying asynchronous modules for these circuits is presented. This method allows bounded gate delays to be included in a two-level modelling mechanism.

Design and verification of a highly concurrent machine

Abstract SPACE is introduced as a new type of computer architecture, capable of very fast simulation of highly concurrent systems. The machine is designed to be scalable, constructed from a vast array of boards. The decisions made in the design of the board are discussed, and the actual hardware (based on an array of field programmable gate array chips) is described. It is shown that SPACE can be programmed by translating a subset of the language Occam into asynchronous digital logic circuits. The handshake protocol used in these circuits is described and examples are given of circuit components which implement Occam operators. Finally, the method by which these circuit components are formally verified using the Circal process algebra is presented.

An Automated Proof Technique for Finite-State Machine Equivalence

This paper presents a mechanical technique which allows behavioural equivalence proof between (nondeterministic) finite-state machines (FSMs). Given a pair of FSMs which are recursively described in the syntax of a process algebra, a third FSM which represents the concurrent behaviour of the two original FSMs is constructed. An algorithm is engineered for comparing the two FSMs against this third concurrent FSM. A self-evident proof of the equivalence between the FSMs will be produced; if the two FSMs are not equivalent, a sequnce of events will be returned which distinguishes between them.

A Learning Circuit That Operates by Discrete Means

Since biological neural systems are assumed to operate by means of techniques that are at least partly analogue, this creates a disjunction between the domain of neural nets and existing binary circuit technology. An alternative is to produce a non-biological neural net model that is suitable for implementation on digital hardware. Using the ideas of back propagation, cellular automata and the process algebra CIRCAL, the authors have investigated a model suitable for VLSI fabrication.