George Kutty

A graphical interval logic for specifying concurrent systems

This article describes a graphical interval logic that is the foundation of a tool set supporting formal specification and verification of concurrent software systems. Experience has shown that most software engineers find standard temporal logics difficult to understand and use. The objective of this article is to enable software engineers to specify and reason about temporal properties of concurrent systems more easily by providing them with a logic that has an intuitive graphical representation and with tools that support its use. To illustrate the use of the graphical logic, the article provides some specifications for an elevator system and proves several properties of the specifications. The article also describes the tool set and the implementation.

A graphical environment for the design of concurrent real-time systems

Concurrent real-time systems are among the most difficult systems to design because of the many possible interleavings of events and because of the timing requirements that must be satisfied. We have developed a graphical environment based on Real-Time Graphical Interval Logic (RTGIL) for specifying and reasoning about the designs of concurrent real-time systems. Specifications in the logic have an intuitive graphical representation that resembles the timing diagrams drawn by software and hardware engineers, with real-time constraints that bound the durations of intervals. The syntax-directed editor of the RTGIL environment enables the user to compose and edit graphical formulas on a workstation display; the automated theorem prover mechanically checks the validity of proofs in the logic; and the database and proof manager tracks proof dependencies and allows formulas to be stored and retrieved. This article describes the logic, methodology, and tools that comprise the prototype RTGIL environment and illustrates the use of the environment with an example application.

Interval logics and their decision procedures: part I: an interval logic

Abstract We present an interval logic, called future interval logic (FIL), for the specification and verification of concurrent systems. Interval logics allow reasoning to be carried out at the level of time intervals, rather than instants. However, unlike some other interval logics, the primitive objects in our semantic model for FIL are not intervals, but instants. An intervals is formed by identifying its end-points, which are instants satisfying given properties. The logic has an intuitive graphical representation, resembling the back-of-the-envelope timing diagrams that designers often draw to reason about concurrent interacting systems. The logic is designed to be insensitive to finite stuttering (a property that facilitates refinement-based multi-level correctness proofs), and is exactly as expressive as the fragment of propositional temporal logic with “until” but no “next”. As the main result of this paper, we show that FIL is elementarily decidable by reduction to the emptiness problem for Buchi Automata. For most other interval logics the decision problem is at best non-elementary and often undecidable. We cosider an extension of FIL with past operators and show that this extension leads to non-elementariness. In a companion paper, we extend the logic to real-time and investigate the decision problem for that extension.

An Automata-Theoretic Decision Procedure for Future Interval Logic

Graphical Interval Logic (GIL) is a temporal logic in which all reasoning is done by means of diagrammatic formulae. It is a discrete linear-time modal logic in which the basic temporal modality is the interval. Future Interval Logic (FIL) provides the logical foundation for GIL. In this paper we present an automata-theoretic decision procedure for FIL with complexity DTIME\((2^{O(n^k )} )\), where n is the size of the formula and k is the depth of interval nesting. For formulae with bounded depth but length unbounded, the satisfiability problem for FIL is shown to be PSPACE-complete. We believe that this is the first result giving a direct decision procedure of elementary complexity for an interval logic. We also show that the logic is transparent to finite stuttering over the class of ω-sequences, a feature that is useful for composition and refinement.

Interval logics and their decision procedures: Part II: a real-time interval logic

Abstract In a companion paper, we presented an interval logic, and showed that it is elementarily decidable. In this paper we extend the logic to allow reasoning about real-time properties of concurrent systems; we call this logic real-time future interval logic (RTFIL). We model time by the real numbers, and allow our syntax to state the bounds on the duration of an interval. RTFIL possesses the “real-time interpolation property,” which appears to be the natural quantitative counterpart of invariance under finite stuttering. As the main result of this paper, we show that RTFIL is decidable; the decision algorithm is slightly more expensive than for the untimed logic. Our decidability proof is based on the reduction of the satisfiability problem for the logic to the emptiness problem for timed Buchi automata. The latter problem was shown decidable by Alur and Dill in a landmark paper, in which this real-time extension of ω-automata was introduced. Finally, we consider an extension of the logic that allows intervals to be constructed by means of “real-time offsets”, and show that even this simple extension renders the logic highly undecidable.

A Real-Time Interval Logic and Its Decision Procedure

Real-Time Future Interval Logic is a visual logic in which formulae have a natural graphical representation, resembling timing diagrams. It is a dense real-time temporal logic that is based on two simple temporal primitives: interval modalities for the purely qualitative part and duration predicates for the quantitative part. We give a decision procedure for the logic by reduction to the emptiness problem for Timed Buchi Automata. The decision procedure forms the core of a proof checker for the logic that we have recently implemented. The logic does not admit instantaneous states, and is invariant under realtime stuttering. These properties facilitate proof methods based on abstraction and refinement. Two natural extensions of the logic lead to nonelementariness and undecidability.

A Graphical Interval Logic Toolset for Verifying Concurrent Systems

Graphical Interval Logic is the foundation of a toolset we have developed to support formal specification and verification of concurrent systems. The logic is a discrete linear-time temporal logic with the distinguishing feature that formulas in the logic have an intuitive graphical representation. The toolset includes a graphical editor that allows the user to compose and edit graphical formulas on a workstation display and a theorem prover that mechanically checks the validity of proofs in the logic. This paper describes the toolset and illustrates its use.

Visual tools for temporal reasoning

We describe a prototype toolkit for reasoning about Graphical Interval Logic (GIL) specifications of concurrent systems. GIL is a visual temporal logic that is intended to be more intuitive and easier to use than standard textual temporal logics. The GIL toolkit helps system designers to create graphical specifications of concurrent systems, to verify properties of those systems from their specifications, and to generate models that satisfy the specifications. The toolkit provides a visual interface with specifications, proofs, and models all depicted graphically. The paper describes the toolkit, discusses its implementation, and provides an illustration of its use.<<ETX>>

Really visual temporal reasoning

Real-Time Future Interval Logic (RTFIL) is a visual logic with formulae that resemble timing diagrams. It is a dense real-time temporal logic that is based on two simple temporal primitives: interval modalities for the purely qualitative part and duration predicates for the quantitative part. We present the logic, and illustrate its use in specifying the railroad crossing example and in proving some of its properties. The logic is decidable by reduction to the emptiness problem of Timed Buchi Automata. An automated theorem prover based on this decision procedure has been implemented as part of a graphical proof environment. The proofs of the railroad crossing example have been verified using this theorem prover. An automated theorem prover and a graphical specification language greatly facilitate the task of verifying real-time proofs. This convenience apart, RTFIL is invariant under real-time stuttering and does not admit instantaneous states. These properties facilitate proof methods based on abstraction and refinement.<<ETX>>

The Real-Time Graphical Interval Logic Toolset

Our experience in using the RTGIL tools has shown that these tools and the graphical representation of the logic are very helpful for specifying and verifying properties of concurrent real-time systems. In addition to the aircraft example, we have used these tools to specify and verify properties of a railroad crossing system, a robot, an alarm system, and a four-phase handshaking protocol.