Georgios I. Orfanoudakis

Nearest-Vector Modulation Strategies With Minimum Amplitude of Low-Frequency Neutral-Point Voltage Oscillations for the Neutral-Point-Clamped Converter

This paper investigates the problem of low-frequency voltage oscillations that appear at the neutral point (NP) of a three-level neutral-point-clamped (NPC) converter. Starting with a detailed analysis of their origin, the paper derives the minimum amplitude of these oscillations that can be achieved by nearest-vector (NV) modulation strategies. It then proves that the criterion of the direction of dc-link capacitor imbalance, which is commonly adopted by NV strategies for performing the task of capacitor balancing, poses a barrier in achieving this minimum. A new criterion is proposed instead, together with an algorithm that incorporates it into existing NV strategies. For the case of NPC inverters operating as motor drives, the resulting reduction in the amplitude of NP voltage oscillations ranges from 30% to 50%. The approach has the advantage of avoiding the significant increment in switching losses and output voltage harmonic distortion, caused by other methods. Simulations in MATLAB-Simulink are used to illustrate its operation and verify that it offers the claimed benefit.

Hybrid Modulation Strategies for Eliminating Low-Frequency Neutral-Point Voltage Oscillations in the Neutral-Point-Clamped Converter

Nearest vector (NV) modulation strategies for the neutral-point-clamped converter are known to generate low-frequency neutral point (NP) voltage oscillations. Non-NV strategies can eliminate these oscillations, but at the expense of higher switching losses and output voltage harmonic distortion. This letter proposes a simple way of creating hybrid strategies, as combinations of NV and non-NV strategies, which are also able to eliminate NP voltage oscillations. The approach minimizes the participation of non-NV strategies and hence their drawbacks, while it can be applied to any type of load (nonlinear and/or unbalanced). Simulations in MATLAB-Simulink are used to illustrate its operation.

Analysis of DC-Link capacitor losses in three-level neutral point clamped and cascaded H-Bridge voltage source inverters

Loss estimation is a critical aspect of inverter design. The present work investigates the losses occurring in the DC-link capacitors of the three-phase three-level Neutral Point Clamped and Cascaded H-Bridge inverter topologies, by performing a harmonic analysis of the capacitor currents. Results are verified by simulations. Their analysis reveals the advantage of the NPC inverter.

7. Design and Control of a Grid-Connected Interleaved Inverter

This paper is concerned with the design and control of a three-phase voltage source grid-connected interleaved inverter. This topology enables the use of low-current devices capable of switching at high frequency, which together with the ripple cancelation feature reduces the size of the output filter and the inverter considerably compared to an equivalent classical two-level voltage source inverter with an LCL output filter using high-current devices with considerably lower switching frequency. Due to its higher switching frequency and low-filter component values, the interleaved inverter also has a much higher bandwidth than the classical inverter, which improves grid voltage harmonics disturbance rejection and increases the speed of response of the inverter and its capability to ride through grid disturbance (e.g., voltage sags and swells). The paper discusses the selection of the number of channels and the filter component values of the interleaved inverter. The design of the digital control system is then discussed in detail. Simulation and practical results are presented to validate the design and demonstrate its capabilities.