Georgios K. Konstadinidis

Implementation of a third-generation 1.1GHz 64b microprocessor

This third-generation 1.1-GHz 64-bit UltraSPARC microprocessor provides 1-MB on-chip level-2 cache, 4-Gb/s off chip memory bandwidth, and a new 200 MHz JBus interface that supports one to four processors. The 87.5-million transistor chip is implemented in a seven-layer-metal copper 0.13-/spl mu/m CMOS process and dissipates 53 W at 1.3 V and 1.1 GHz.

Implementation of a Third-Generation 16-Core 32-Thread Chip-Multithreading SPARCs® Processor

This third-generation chip-multithreading (CMT) SPARC processor is targeted for high-performance servers, and is optimized for both single- and multi-threaded applications. The architecture highlights are provided in [M. Tremblay and S. Chaudhry, 2008], while this paper focuses on the physical implementation aspects, providing an overview of circuit innovations in memory arrays, register files, and floating-point hardware that boost the performance and circuit robustness with low area overhead. The 396mm2 chip is fabricated in a 11M 65nm CMOS process and operates at a nominal frequency of 2.3GHz, consuming a maximum power of 250W at 1.2V. Power-management techniques include clock gating at core-cluster level and power throttling through a single-thread-issue mode of operation. This mode is used in power-constrained systems without sacrificing single-thread performance.

Timing window applications in UltraSPARC-IIIi/spl trade/ microprocessor design

This paper presents two timing window methodologies used in UltraSPARC-IIIi/spl trade/ microprocessor design. They have improved the accuracy of timing and noise analysis. In timing analysis, timing windows are applied to calculate effective Miller factors of coupling nets; in noise analysis, they are applied to waive false noise violations. Results show that by using timing windows in timing analysis, 72% of the CPU-level nets have more accurate Miller factors. Thus, it reduces the number of false timing paths. During the development of this application, a simple and practical convergence rule is defined to stop the iteration. Also, the timing window application on noise analysis has identified 42% of the CPU-level noise violations which can be waived in UltraSPARC-IIIi/spl trade/ chip. This significantly improved the productivity of the design.

Challenges in microprocessor physical and power management design

The free ride from process technology for CPU design has ended. Innovations in architecture, circuit design, and physical implementation are required to cope with increased challenges imposed by the lack of process scaling, increased variability and layout-dependent effects. In addition, power density is rising to prohibitive levels and has now become the predominant performance limiter. Extensive power management at both architectural and circuit levels is a major focus point in todays microprocessor design. This paper will give an overview of the issues, the potential solutions and the tool requirements to address the ever- increasing physical design and power management challenges.

Physical Design Considerations

Optimization of the structural skew alone, through balanced H or grid clock design and load balancing, is not adequate. Process, voltage, and temperature (PVT) variations dominate in most cases the total clock skew.While active deskew circuits [1–8] (also thoroughly described in Chaps.2 and 7, and the use of asynchronous FIFOs in clock domain crossings [9] can reduce the effect of skew, we still need to reduce the variation in the clock network to minimize the overall complexity and design effort. Higher skew would require larger number and extended range in the deskewing circuits. Increased clock skew would mean larger hold time violations that would require additional delay elements inserted in the critical path. This will increase area and power. This chapter focuses on physical design considerations to help minimize overall skew and to avoid overdesign. At first, we provide an overview of various skew components and explain their dependency on the process, voltage, and temperature variations. We describe the main sources of transistor variation including lithographic, layout, proximity, and strain related effects. Similarly, interconnects suffer from lithographic, process, and pattern density effects that add to the variability. We provide recommendations on how to optimize the layout to minimize both the transistor and interconnect variations, and provide answers to fundamental clock designer questions: How should I calculate the total process variation along a chain of clock buffers? Should I just add the variations of the individual stages or should I use a Root Mean Square approach? (It turns out none of the above approaches is correct if used in isolation.) What is the best approach in dealing with the voltage variation? Do all clock buffers see the same voltage variation? How does the temperature variation affect clock skew, and are there ways to compensate for this? What is the impact of inductance? Good understanding of the behavior of correlated vs. noncorrelated parameters will help us define the correct methodology for the delay variation estimation using well-established statistical techniques.