Georgios Zervakis

Design-Efficient Approximate Multiplication Circuits Through Partial Product Perforation

Approximate computing has received significant attention as a promising strategy to decrease power consumption of inherently error tolerant applications. In this paper, we focus on hardware-level approximation by introducing the partial product perforation technique for designing approximate multiplication circuits. We prove in a mathematically rigorous manner that in partial product perforation, the imposed errors are bounded and predictable, depending only on the input distribution. Through extensive experimental evaluation, we apply the partial product perforation method on different multiplier architectures and expose the optimal architecture-perforation configuration pairs for different error constraints. We show that, compared with the respective exact design, the partial product perforation delivers reductions of up to 50% in power consumption, 45% in area, and 35% in critical delay. In addition, the product perforation method is compared with the state-of-the-art approximation techniques, i.e., truncation, voltage overscaling, and logic approximation, showing that it outperforms them in terms of power dissipation and error.

Flexible DSP Accelerator Architecture Exploiting Carry-Save Arithmetic

Hardware acceleration has been proved an extremely promising implementation strategy for the digital signal processing (DSP) domain. Rather than adopting a monolithic application-specific integrated circuit design approach, in this brief, we present a novel accelerator architecture comprising flexible computational units that support the execution of a large set of operation templates found in DSP kernels. We differentiate from previous works on flexible accelerators by enabling computations to be aggressively performed with carry-save (CS) formatted data. Advanced arithmetic design concepts, i.e., recoding techniques, are utilized enabling CS optimizations to be performed in a larger scope than in previous approaches. Extensive experimental evaluations show that the proposed accelerator architecture delivers average gains of up to 61.91% in area-delay product and 54.43% in energy consumption compared with the state-of-art flexible datapaths.

Approximate Multiplier Architectures Through Partial Product Perforation: Power-Area Tradeoffs Analysis

Approximate computing has received significant attention as a promising strategy to decrease power consumption of inherently error-tolerant applications. Hardware approximation mainly targets arithmetic units, e.g. adders and multipliers. In this paper, we design new approximate hardware multipliers and propose the Partial Product Perforation technique, which omits a number of consecutive partial products by perforating their generation. Through extensive experimental evaluation, we apply the partial product perforation method on different multiplier architectures and expose the optimal configurations for different error values. We show that the partial product perforation delivers reductions of up to 50% in power consumption, 45% in area and 35% in critical delay. Also, the product perforation method is compared with state-of-the-art works on approximate computing that consider the Voltage Over-Scaling (VOS) and logic approximation (i.e. design of approximate compressors) techniques, outperforming them in terms of power dissipation by up to 17% and 20% on average respectively. Finally, with respect to the aforementioned gains, the error value delivered by the proposed product perforation method is smaller by 70% and 99% than the VOS and logic approximation methods respectively.

Performance-power exploration of software-defined big data analytics: The AEGLE cloud backend

In this paper, we present the design and analyze the performance-energy characteristics of a software-defined infrastructure targeting Big Data analytics workloads. This software-defined Big Data framework forms the data analytic platform adopted in AEGLE1, an European H2020 funded project for healthcare analytics. The developed framework utilizes state-of-art open source solutions and it is very flexible to enable the definition and automatic deployment of differing SPARK over Hadoop cluster configurations as analytics engines. In this paper, we exploit this flexibility of our software defined infrastructure to explore the performance-energy trade-offs of Big Data analytics under variable resource allocation scenarios. Specifically, we show that with respect to our local infrastructure, i.e., two Intel Xeon E5-2658A servers with 128GB RAM each, virtual cluster configurations with many nodes achieve the highest performance, while virtual cluster with high available RAM memory are more power efficient, exhibiting higher instructions per cycle (IPC) per kilojoule values.

Delta DICE: A Double Node Upset resilient latch

In this paper we propose the novel Delta DICE latch that is tolerant to SNUs (Single Node Upsets) and DNUs (Double Node Upsets). The latch comprises three DICE cells in a delta interconnection topology, providing enough redundant nodes to guarantee resilience to conventional SNUs, as well as DNUs due to charge sharing. Simulation results demonstrated that in terms of power dissipation and propagation delay, the Delta DICE latch outperforms BISER-based latches that are SNU or DNU tolerant and provides DNU resilience at a small energy×delay penalty compared to other SNU tolerant cells.

Hybrid approximate multiplier architectures for improved power-accuracy trade-offs

Approximate computing forms a promising design alternative for inherently error resilient applications, trading accuracy for power savings. In this paper, we exploit multi-level approximation, i.e. at the algorithmic, the logic and the circuit level, to design low power approximate arithmetic architectures for hardware multipliers. Motivated from the limited power savings that approximation techniques can achieve in isolation, we explore hybrid methods that apply simultaneously more than one techniques from different layers. We introduce the concept of perforation for approximate arithmetic circuit design and we explore the newly defined design space of hybrid designs showing that it leads to lower power consumption at every examined error range. To address the increased complexity of the target design space, we introduce an heuristic optimization technique and the corresponding design framework that automatically generates hybrid low-power approximate multipliers requiring a small number of design evaluations, i.e. synthesis, simulation, power and timing analysis. Through extensive experimentation, we show that the proposed techniques converge towards optimal solutions and deliver approximate designs that are always more efficient with respect to state-of-art approaches. Power savings of 11% are reported for small error bounds and more than 30% in case of more relaxed error constraints.

A high radix montgomery multiplier with concurrent error detection

Modular multiplication is essential in cryptographic algorithms (e.g. RSA), as it determines the performance of the entire cryptographic operation and its reliability is crucial for the system security. In this paper, we propose a high-radix Montgomery Modular Multiplication (MMM) implementation and conduct an exploration to find the optimal radix. Also, a concurrent error detection circuit with 99.9% detection rate, small area and power overheads (2.24% and 1.46% respectively) is proposed to protect the MMM against fault attacks and natural faults.

High performance MAC designs

In this paper we propose two high performance multiplication-accumulation (MAC) designs. Targeting to operate at higher frequency, we investigate two different techniques based on the carry-save representation in order to reduce the delay impact of the accumulation process on the MAC operation. We conducted detailed experimental measurements to verify the advantages of the proposed MAC designs compared to two existing ones. Both the proposed designs operate at higher frequency without any losses in the area occupied or the power consumed.

An independent dual gate SOI FinFET soft-error resilient memory cell

In this paper we present an 8T footless storage element, the FFDICE (FinFET DICE), a dual interlocked structure using Independent Gate SOI FinFET transistors that exhibits soft error resilience characteristics. Compared to the conventional DICE cell, the proposed design achieves area savings by dispensing with the four NMOS driver transistors, retains the excellent tolerance characteristics to single node upsets and similar multiple node upset resilience. Of significance to modern designs that apply voltage scaling techniques to achieve power savings, simulation results on Static Voltage Noise Margin and Static Current Noise Margin metrics show that the proposed cell exhibits excellent stability across an examined voltage range of 0.75V to 1V.

Energy-Efficient Acceleration of Spark Machine Learning Applications on FPGAs

Emerging applications like machine learning, graph computations, and generally big data analytics require powerful systems that can process large amounts of data without consuming high power. Furthermore, such emerging applications require fast time-to-market and reduced development times. So to address the large processing requirements of these applications, novel architectures are required in the domain of high-performance and energy-efficient processors.