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Dive into the research topics where Gerard Allwein is active.

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Featured researches published by Gerard Allwein.


Software and Systems Modeling | 2004

Using DAG transformations to verify Euler/Venn homogeneous and Euler/Venn FOL heterogeneous rules of inference

Nik Swoboda; Gerard Allwein

In this paper we will present a graph-transformation based method for the verification of heterogeneous first order logic (FOL) and Euler/Venn proofs. In previous work, it has been shown that a special collection of directed acyclic graphs (DAGs) can be used interchangeably with Euler/Venn diagrams in reasoning processes. Thus, proofs which include Euler/Venn diagrams can be thought of as proofs with DAGs where steps involving only Euler/Venn diagrams can be treated as particular DAG transformations. Here we will show how the characterization of these manipulations can be used to verify Euler/Venn proofs. Also, a method for verifying the use of heterogeneous Euler/Venn and FOL reasoning rules will be presented that is also based upon DAG transformations .


Theoretical Computer Science | 2010

Algebraic Information Theory For Binary Channels

Keye Martin; Ira S. Moskowitz; Gerard Allwein

We study the algebraic structure of the monoid of binary channels and show that it is dually isomorphic to the interval domain over the unit interval with the operation from Martin (2006) [4]. We show that the capacity of a binary channel is Scott continuous as a map on the interval domain and that its restriction to any maximally commutative submonoid of binary channels is an order isomorphism onto the unit interval. These results allows us to solve an important open problem in the analysis of covert channels: a provably correct method for injecting noise into a covert channel which will reduce its capacity to any level desired in such a way that the practitioner is free to insert the noise at any point in the system.


languages compilers and tools for embedded systems | 2015

Semantics Driven Hardware Design, Implementation, and Verification with ReWire

Adam M. Procter; William L. Harrison; Ian Graves; Michela Becchi; Gerard Allwein

There is no such thing as high assurance without high assurance hardware. High assurance hardware is essential, because any and all high assurance systems ultimately depend on hardware that conforms to, and does not undermine, critical system properties and invariants. And yet, high assurance hardware development is stymied by the conceptual gap between formal methods and hardware description languages used by engineers. This paper presents ReWire, a functional programming language providing a suitable foundation for formal verification of hardware designs, and a compiler for that language that translates high-level, semantics-driven designs directly into working hardware. ReWires design and implementation are presented, along with a case study in the design of a secure multicore processor, demonstrating both ReWires expressiveness as a programming language and its power as a framework for formal, high-level reasoning about hardware systems.


international conference on formal engineering methods | 2012

The confinement problem in the presence of faults

William L. Harrison; Adam M. Procter; Gerard Allwein

In this paper, we establish a semantic foundation for the safe execution of untrusted code. Our approach extends Moggis computational λ-calculus in two dimensions with operations for asynchronous concurrency, shared state and software faults and with an effect type system a la Wadler providing fine-grained control of effects. An equational system for fault isolation is exhibited and its soundness demonstrated with a semantics based on monad transformers. Our formalization of the equational system in the Coq theorem prover is discussed. We argue that the approach may be generalized to capture other safety properties, including information flow security.


conference on domain specific languages | 2009

Model-Driven Engineering from Modular Monadic Semantics: Implementation Techniques Targeting Hardware and Software

William L. Harrison; Adam M. Procter; Jason Agron; Garrin Kimmell; Gerard Allwein

Recent research has shown how the formal modeling of concurrent systems can benefit from monadic structuring. With this approach, a formal system model is really a program in a domain specific language defined by a monad for shared-state concurrency. Can these models be compiled into efficient implementations? This paper addresses this question and presents an overview of techniques for compiling monadic concurrency models directly into reasonably efficient software and hardware implementations. The implementation techniques described in this article form the basis of a semantics-directed approach to model-driven engineering.


Journal of Visual Languages and Computing | 2008

A formalism for visual security protocol modeling

J. McDermott; Gerard Allwein

Existing visual modeling paradigms do not adequately cover the visual modeling of security protocols: sequences of interactions between principals in a security system. A visual formalism for security protocol modeling should not only be well-defined but also satisfy certain pragmatic criteria: support for compositional, comprehensive, laconic, and lucid models. Candidate techniques from the OMGs Model Driven Architecture, based largely on UML 2.0, lack a formal syntax and semantics. Well-defined visual formalisms outside of UML have shortcomings with respect to one or more of the pragmatic criteria. We present the GSPML visual formalism as a solution that satisfies all of the pragmatic criteria. We show that GSPML is well-defined with structural operational semantics and a hypergraph grammar syntax.


applied reconfigurable computing | 2015

Hardware Synthesis from Functional Embedded Domain-Specific Languages: A Case Study in Regular Expression Compilation

Ian Graves; Adam M. Procter; William L. Harrison; Michela Becchi; Gerard Allwein

Although FPGAs have the potential to bring software-like flexibility and agility to the hardware world, designing for FPGAs remains a difficult task divorced from standard software engineering norms. A better programming flow would go far towards realizing the potential of widely deployed, programmable hardware. We propose a general methodology based on domain specific languages embedded in the functional language Haskell to bridge the gap between high level abstractions that support programmer productivity and the need for high performance in FPGA circuit implementations. We illustrate this methodology with a framework for regular expression to hardware compilers, written in Haskell, that supports high programmer productivity while producing circuits whose performance matches and, indeed, exceeds that of a state of the art, hand-optimized VHDL-based tool. For example, after applying a novel optimization pass, throughput increased an average of \(28.3\,\%\) over the state of the art tool for one set of benchmarks. All code discussed in the paper is available online [1].


Lecture Notes in Computer Science | 2004

Diagrams and Non-monotonicity in Puzzles

Benedek Nagy; Gerard Allwein

Liar puzzles have been popularized by Raymond Smullyan in several books. This paper presents a logical and diagrammatic examination of such puzzles in terms of a epistemic truth values. Also, non-monotonic reasoning may occur as new information is learned about a puzzle. This paper presents a way to think about such non-monotonic reasoning which does not involve the use of a non-monotonic logic but instead utilizes context shifts among static logics. The information coming from the presented diagrams is timeless, it is a monotonic back-bone of the whole non-monotonic knowledge.


field-programmable technology | 2015

Provably Correct Development of reconfigurable hardware designs via equational reasoning

Ian Graves; Adam M. Procter; William L. Harrison; Gerard Allwein

There is a semantic gap between the hardware definition languages used to design and implement hardware and the languages and logics used to formally specify and verify them. Bridging this gap-i.e., constructing formal models from existing hardware artifacts-can be costly, time-consuming, and error prone-and yet utterly necessary if formal verification is to proceed. This work demonstrates that this gap can be collapsed by starting in a pure functional language that is also a hardware description language, and that equational style verifications may be performed directly on the source text of a hardware design, thereby significantly lowering the verification cost for reconfigurable designs. When combined with an efficient compiler, this methodology achieves both good performance and low cost verification.


reconfigurable communication centric systems on chip | 2016

A programming model for reconfigurable computing based in functional concurrency

William L. Harrison; Ian Graves; Adam M. Procter; Michela Becchi; Gerard Allwein

FPGA programmability remains a concern with respect to the broad adoption of the technology. One reason for this is simple: FPGA applications are frequently implementations of concurrent algorithms that could be most directly rendered in concurrent languages, but there is little or no first-class support for concurrent applications in conventional hardware description languages. It stands to reason that FPGA programmability would be enhanced in a hardware description language with first-class concurrency. The starting point for this paper is a functional hardware description language with built-in support for concurrency called ReWire. Because it is a concurrent functional language, ReWire supports the elegant expression of common concurrency paradigms; we illustrate this with several case studies.

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Ian Graves

University of Missouri

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Ira S. Moskowitz

United States Naval Research Laboratory

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Nik Swoboda

Technical University of Madrid

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Hilmi Demir

United States Naval Research Laboratory

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J. McDermott

United States Naval Research Laboratory

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