Gerard Boudon

A BiCMOS circuit family for a 0.45 mu m CMOS/BiCMOS sea of gates

A BiCMOS standard cell circuit library is mixed in an existing 300 K-CMOS ASIC (application-specific integrated circuit) sea of gates featuring 0.45- mu m L/sub eff/ FETs. The 3.6-V BiCMOS circuits with a 15-GHz NPN are compatible in voltage levels with the CMOS. Various terminator/level shifter BiCMOS circuits permit performance from 180 ps to 220 ps. A Booth/Wallace tree 16*16 multiplier and an array of 2700 AND-ORs for a noise experiment have been implemented on a 86 K, 6.7-mm chip.<<ETX>>

Multi-emitter BiCMOS logic circuit family

It has been demonstrated that, in a 64-b carry look-ahead adder, the use of conventional half-micron BiCMOS circuits under a 3.6-V power supply gives 40% faster delay than the CMOS design. Up to 85% improvement is obtained with the new multiemitter BiCMOS circuit. A complete logic circuit family with the multiemitter concept is described, showing a maximum benefit on gates with a high number of inputs

Internal ECL-BiCMOS translator circuits in half micron technology

BiCMOS associates high-speed circuits with the low power requirements of CMOS. Traditional BiCMOS circuits are mainly CMOS-based with bipolar buffers to improve driving capability and speed. Increased performance can be obtained with BiCMOS technology if CMOS/BiCMOS circuits are merged with an ECL (emitter-coupled logic) low swing circuit. Mixing of logic is possible if very-high-speed level translators for levels conversion are designed. The benefits of such an approach in 0.5- mu m BiCMOS technology have been estimated for the proposed ECL-to-CMOS-level convertor circuits.<<ETX>>

A 30ns-32b programmable arithmetic operator

This paper will cover a programmable arithmetic operator implemented in a 6.9×7.1mm gate array chip containing 6000 logic ceils, dissipating less than 1W. The measured gate array is 200ps in a 0.5μm CMOS technology.

A 800 MHz PowerPC SOC with PCI-X DDR266, DDRII-667, and RAID assist

A PowerPC system-on-a-chip processor which integrates high speed state of the art 800 MHz PowerPC, DDRII-667 memory controller, RAID assist logic, and three PCI-X DDR266 interfaces with a rich mix of conventional peripherals is described. The PowerPC, with on-chip L2 cache enabled, executes up to 1600 DMIPS. The RAID assist logic is capable of transferring 2 Gbytes/sec. The state of the art PowerPC, the high bandwidth data pipes, and the RAID assist logic make the SOC an ideal solution for RAID controller applications. Active power consumption is as low as 6W with a 1.5 volt supply. The SOC has been implemented in a 0.13 /spl mu/m, 1.5 V nominal-supply, bulk CMOS process.

Multiemitter BiCMOS logic circuit family

It has been demonstrated that, in a 64-b carry look-ahead adder, the use of conventional half-micron BiCMOS circuits under a 3.6-V power supply gives 40% faster delay than the CMOS design. Up to 85% improvement is obtained with the new multiemitter BiCMOS circuit. A complete logic circuit family with the multiemitter concept is described, showing a maximum benefit on gates with a high number of inputs