Gereon Vogtmeier

A CMOS photodiode array with in-pixel data acquisition system for computed tomography

A CMOS photodetector array with in-pixel electronics has been developed for computed tomography (CT) applications. Current CT detectors are based on two discrete components: a photodiode array and a data acquisition system (amplifier). Both elements have to fulfill a series of severe requirements. CT scanners are moving toward larger detectors and higher speed, and yet lowering costs and improving performance. This contribution relates to the integration of both elements into a standard CMOS process to fulfill future CT scanner specifications and for a cost-effective solution. A series of limitations have been overcome to integrate both the photodiode and a charge-sensing amplifier at pixel level. In order to balance the limited responsivity of standard CMOS photodiodes, a new low-capacitance device has been devised so that low-noise design is possible while providing enough gain in the amplifier. Since a good geometric detective quantum efficiency is desired (>60%), the available area for electronics is very limited. In order to achieve a necessary dynamic range of 17 bits in such reduced area, a single-stage amplifier with automatic gain-switching has been devised. Consisting of a 10/spl times/20 pixel array, in-pixel electronics has been designed to achieve a quantum limited system under CT operating conditions.

Two-dimensional anti-scatter grids for computed tomography detectors

The use of two-dimensional, focused, anti-scatter-grids (ASGs) in computed tomography is one essential solution to reduce the scatter radiation for large area detectors. A detailed analysis of the requirements and related image quality aspects lead to the specification of the two-dimensional focused geometry of the X-ray absorbing grids. Scatter simulations indicated trade-off conditions and provided estimations for the expected scatter reduction performance. Different production technologies for focused two-dimensional structures have been evaluated. The presented technology of Tomo Lithographic Molding (TomoTM) shows good fulfilment of the specifications. TomoTM is a synthesis of lithographic micromachining, precision stack lamination, molding, and casting processes with application-specific material systems. Geometry, material properties, and scatter performance have been investigated. Different analysis methods will be presented and results of the investigations demonstrate the performance capability of this two-dimensional grid technology. Material composition of the tungsten-polymer composite, homogeneity of wall thickness, and precision of the focusing have the biggest influence on the X-ray behavior. Dynamic forces on the anti-scatter-grid during CT operations should not lead to dynamic shadowing or intensity modulation on the active pixel area. Simulations of the wall deformation have been done to estimate the maximum position deviation. Prototype two-dimensional ASGs have been characterized and show promising results.

Low noise, large area CMOS x-ray image sensor for C.T. application

In this paper, we describe a novel CMOS X-ray active pixel sensor for indirect C.T. X-ray detection. Considerable noise reduction has been achieved by lowering the detector junction capacitance. For this purpose a new low capacitance, low dark current dot type photodiode based on minority diffusion has been developed. The dynamic range is expanded to 17 bit by the use of individual in-pixel automatic gain control. A photon noise limited detector exhibiting a 20 /spl times/ 10 pixel array with a frame rate of 3000 frames/sec has been realized in a 1.2 /spl mu/m CMOS process.

An In-Pixel Current-Mode Amplifier for Computed Tomography

A high-dynamic-range current-mode detector for a computed-tomography application is shown. A regulated current-mirror structure that provides a 17-bit dynamic range and a noise floor below 3 pArms has been implemented at pixel level. Nonlinearity is kept below 2%, and the signal bandwidth is higher than 10 kHz. A test structure with a 4 times 4 pixel array is presented in this paper. Both the photodiode and the current-mode amplifier have been integrated into the same CMOS standard process

A high dynamic range, high linearity CMOS current-mode image sensor for computed tomography

In this work, we show a high dynamic range current-mode detector for computer tomography application. A regulated current mirror structure has been implemented at pixel level that provides with 17 bits dynamic range and a noise floor below 3 pA/sub RMS/. Non-linearity is kept below 2% and signal bandwidth is higher than 10 kHz. A test structure with 4/spl times/4 pixel array is presented is this paper. Both photodiode and current mode amplifier have been integrated into the same CMOS standard process.

A CMOS photodiode array with in-pixel data acquisition system

A CMOS photodetector array with in-pixel electronics has been developed for computed tomography (CT) applications. Consisting of 10/spl times/20 pixel array in-pixel electronics has been designed to achieve 17 bits dynamic range and a quantum limited system under CT operating range. A series of limitations have been overcome to integrate both photodiode and a charge-sensing amplifier at pixel level.

CMOS compatible through wafer interconnects for medical imaging detectors

Modern medical imaging systems like computed tomography (CT) require advanced technologies for the imaging sensor and processing electronics as well as for the packaging technologies to build an integrated sensor-system. As the size of the overall detector increased within the last years, new solutions for the realization of these large area detectors are required especially for advanced systems with integrated detector electronics. As the pixel size is about 1.1 times 1.4 mm2 the overall size of the detector, with about 60,000 pixels, is in the range of 76,000 mm2. Several advanced concepts - realized in standard CMOS technology - for active pixel arrays with charge-integration, high dynamic range current amplifier and in-pixel sigma-delta-modulator have been investigated. For the usage in large area detectors new packaging concepts have to be developed as a four-side-buttable (tile) structure can only be realized with a backside connection of the chip. In our development the through wafer interconnects (TWI) do not necessarily show up in the front side as metal signal layers could be used for signal routing on top of the TWI. From CT application the geometric and the electric specifications for the TWI have been derived. The optical sensitive front-side of the chip that is attached to a scintillator crystal is not influenced by the processing of the TWI. The basic idea for the CMOS-compatible TWI technology is the design of interconnecting conductive trench geometries in the wafer prior to the CMOS processing.

Impact of CT detector pixel-to-pixel crosstalk on image quality

In Computed Tomography (CT), the image quality sensitively depends on the accuracy of the X-ray projection signal, which is acquired by a two-dimensional array of pixel cells in the detector. If the signal of X-ray photons is spread out to neighboring pixels (crosstalk), a decrease of spatial resolution may result. Moreover, streak and ring artifacts may emerge. Deploying system simulations for state-of-the-art CT detector configurations, we characterize origin and appearance of these artifacts in the reconstructed CT images for different scenarios. A uniform pixel-to-pixel crosstalk results in a loss of spatial resolution only. The Modulation Transfer Function (MTF) is attenuated, without affecting the limiting resolution, which is defined as the first zero of the MTF. Additional streak and ring artifacts appear, if the pixel-to-pixel crosstalk is non-uniform. Parallel to the system simulations we developed an analytical model. The model explains resolution loss and artifact level using the first and second derivative of the X-ray profile acquired by the detector. Simulations and analytical model are in agreement to each other. We discuss the perceptibility of ring and streak artifacts within noisy images if no crosstalk correction is applied.

Through Wafer Interconnects - A Technology not only for Medical Applications

The foremost driver for the development of fully CMOS compatible Through Wafer Interconnects (TWIs) is the need of very large photodiode arrays for detectors, e.g. in computed tomography applications. The front to back-side contact allows the four-side buttable chip placement of the already large chips (20mm × 22mm 2 ). The TWI technology allows an interconnection for chips up to 280μm thickness. This technique does not require any via opening at the font side, thus enabling a metal signal routing on the active side, on top of the interconnection. The application specific optical sensitive front-side of the chip is fully accessible. The production process is separated into three main steps. The first step is the implementation of the special TWI geometry into the CMOS substrate. Depending on the electrical and geometrical requirements of the circuit, different TWI structures are built with deep trenches (up to 280μm), which are passivated and filled with doped poly-silicon. The technologies used in this process, such as DRIE-etching, oxidation and low pressure CVD, are standard CMOS compatible processes. The use of poly-silicon prevents from achieving very low resistivity interconnections but allows the use of all CMOS process steps for an imager production (no temperature limitation – compared to other TWI process flows). The second step is the standard CMOS processing on the substrate already including the TWIs. The third step is a low temperature back-side process starting with wafer thinning down to 280μm or less to open the implemented TWI structure from the back-side. The thickness may be selected depending on the target application. A modified under ball metallization (UBM) process, which could include also re-routing of signals on the back-side, concludes the process flow until the solder ball placement, or similar bond connections. The special process flow opens a variety of applications which benefit from the full CMOS compatible processing and the accessible front-side.