Gerhard Goos

Register allocation for programs in SSA-Form

As register allocation is one of the most important phases in optimizing compilers, much work has been done to improve its quality and speed. We present a novel register allocation architecture for programs in SSA-form which simplifies register allocation significantly. We investigate certain properties of SSA-programs and their interference graphs, showing that they belong to the class of chordal graphs. This leads to a quadratic-time optimal coloring algorithm and allows for decoupling the tasks of coloring, spilling and coalescing completely. After presenting heuristic methods for spilling and coalescing, we compare our coalescing heuristic to an optimal method based on integer linear programming.

Verification of Compilers

We report about a joint project of the universities at Karlsruhe, Kiel and Ulm on how to get correct compilers for realistic programming languages. Arguing about compiler correctness must strat from a compiling specification describing the correspondence of source and target language in formal terms. We have chosen to use abstract state machines to formalize this correspondence. This allows us to stay with traditional compiler architectures for subdividing the compiler tast. A main achievement is the use of program checking for replacing large parts of compiler verification by the much simpler task of verifying program checkers.

Optimal register allocation for SSA-form programs in polynomial time

This paper gives a constructive proof that the register allocation problem for a uniform register set is solvable in polynomial time for SSA-form programs.

Copy coalescing by graph recoloring

Register allocation is always a trade-off between live-range splitting and coalescing. Live-range splitting generally leads to less spilling at the cost of inserting shuffle code. Coalescing removes shuffle code while potentially raising the register demand and causing spilling. Recent research showed that the live-range splitting of the SSA forms Æ-functions leads to chordal interference graphs. This improves upon two long-standing inconveniences of graph coloring register allocation: First, chordal graphs are optimally colorable in quadratic time. Second, the number of colors needed to color the graph is equal to the maximal register pressure in the program. However, the inserted shuffle code incurred by the Æ-functions can slow down the program severely. Hence, to make such an approach work in practice, a coalescing technique is needed that removes most of the shuffle code without causing further spilling. In this paper, we present a coalescing technique designed for, but not limited to, SSA-form register allocation. We exploit that a valid coloring can be easily obtained by an SSA-based register allocator. This initial coloring is then improved by recoloring the interference graph and assigning shuffle-code related nodes the same color. Thereby, we always keep the coloring of the graph valid. Hence, the coalescing is safe, i. e. no spill code will be caused by coalescing. Comparing to iterated register coalescing, the state of the art in safe coalescing, our method is able to remove 22.5% of the costs and 44.3% of the copies iterated coalescing left over. The best solution possible, found by a colaescer using integer linear programming (ILP), was 35.9% of the costs and 51.9% of the copies iterated coalescing left over. The runtime of programs compiled with our heuristic matches that of the programs compiled with the ILP technique.

A Programming Example

It very often happens that from the structure of the data we are able to predict the division of a problem into subproblems and therefore the program structure. The data may be the input, the output or an intermediate data structure. In some applications — as in our first example — there does not even exist a data structure as a whole but one element after the other is generated and immediately processed.

Experience with an automatic code generator generator

We implemented an automatic code generator generator based on the approach of Glanville and Graham. We describe our experience with this system and compare the generated code with that of a conventional Pascal compiler.

Construction of Verified Compiler Front-Ends with Program-Checking

This paper describes how program-checking can be used to establish the correctness of a compiler front-end which was generated by unverified compiler construction tools. The basic idea of programchecking is to use an unverified algorithm whose results are checked by a verified component at run time. The approach not only simplifies the construction of a verified compiler front-end because checking the result of the analysis is much simpler to verify than the verification of a high sophisticated compiler front-end. It even allows to define a notion of front-end correctness. Furthermore, we are still able to use existing generators tools without major modifications. Additionally, this work points out the tasks which still have to be verified and it discusses the flexibility of the approach.

An attribute grammar for Ada

We describe the development of a formal specification of the static semantics of Ada in form of an attribute grammar. This specification is complete, and was tested extensively with automatically generated equivalent Pascal programs. From this specification we systematically developed the semantic analysis part of our Ada Compiler Front End. We outline the general proceeding when specifying semantic analysis with attribute grammars and then discuss to some extent examples about declaration elaboration and overloading resolution. CR Categories and Subject Descriptors: D.3.1 [Programming Languages]: Formal definitions and Theory - semantics; D.3.4 [Programming Languages]: Processors - Translator writing systems and compiler generators; F.3.2 [Logics and Meanings of Programs]: Semantics of Programming Languages - algebraic approaches to semantics.

Verifix: Konstruktion und Architektur verifizierender Übersetzer (Verifix: Construction and Architecture of Verifying Compilers)

Zusammenfassung Übersetzer (Compiler) sind das Herzstück bei der Erstellung von Software, erlauben sie es doch, Programme in höheren Programmiersprachen zu schreiben, die dann mithilfe von Übersetzern in Maschinencode transformiert werden. Um zuverlässige Software zu erstellen, ist es daher unbedingt erforderlich, dass Übersetzer nachweislich korrekt arbeiten. Das DFG-Projekt Verifix, das gemeinsam in den Arbeitsgruppen von Prof. Goos (Universität Karlsruhe), Prof. v. Henke (Universität Ulm) und Prof. Langmaack (Christian-Albrechts-Universität zu Kiel) durchgeführt wurde, hat Methoden entwickelt, mit denen formal korrekte Übersetzer konstruiert werden können, ohne dass dabei Leistungseinbußen entstehen. In diesem Artikel stellen wir diese Methoden sowie unsere im Projekt erzielten Ergebnisse im Überblick vor.

Verifying Compilers and ASMs or ASMs for Uniform Description of Multistep Transformations

A verifying compiler ensures that the compiled code is always correct but the compiler may also terminate with an error mesage and then fails to generate code. We argue that with respect to compiler correctness this is the best possible result which can be achieved in practice. Such a compiler may even include unverified code provided the results of such code can be proven correct independently from how they are generated.We then show how abstract state machines (ASMs) can be used to uniformly describe the dynamic semantics of the programs being compiled across the various intermediate transformation steps occurring within a compiler. Besides being a convenient tool for describing dynamic semantics the fact that we do not have to switch between difaerent descriptional methods is found to be extremely useful.