Geun Min Choi

Necessity of Cleaning and its Application in Future Memory Devices

Concerning the processes of the semiconductor industry, device integration is increasing and cell structure is becoming more complicated, which brings many new kinds of challenges. The basic requirements for a future integration device are minimum feature size reduction with device integration and high-speed operation with sufficient cell capacitance. Many kinds of conventional films including electrode and dielectric materials should be altered to meet device requirements. Moreover, as the allowance level for contaminants on substrate surfaces becomes more stringent, the importance of removing them becomes even greater. Because of this, the semiconductor process for high quality device fabrication will never be realized without perfect cleaning on all surfaces. It is reported that the conventional cleaning solutions such as a NH4OH/H2O2/H2O (SC-1) solution (1:4:20, 80 °C), H2SO4/H2O2 (SPM) solution (4:1, 90 to 120°C), and HCl/H2O2/H2O (HPM) solution (1:1:6, 80 to 90°C) are not compatible with metal film exposed surfaces with very tiny patterns, due to the fast etching rate of metal films [1] . In 1995, at the base of the mechanism of the removal of the adhered contaminants such as metallic impurities, particles and organics, T. Ohmi proposed a total room temperature wet cleaning process (so called “UCT cleaning”) [2]. As a result of the continuous research on developed cleaning, the five steps process was revised to a four step room temperature wet cleaning for real device cleaning. The cleaning consists of 1) CO2 added O3-UPW cleaning for removing organic and metallic impurities, 2) NH3 added H2-UPW+MS cleaning for removing of particles, 3) HF/H2O2(FPM) cleaning for removing metallic impurities, and 4) H2-UPW+MS rinse for the removal of chemical residues, prevention of particle re-adhesion, suppression of native oxide growth, and enhancement of H-termination.

Evaluation of wafer drying methods for GIGA-LEVEL device fabrication

This study deals with drying induced water marks dependency on the last cleaning methods, substrate conditions, and drying pre-step delaying times, which are supposed to become a big issue with down scaling of device geometry. The data show that water marks induced by drying failure increase with increasing contact angle on the various surfaces. They are mainly composed of either silicon oxide only or silicon oxide with organic compounds. The former is removed by a dilute HF and/or hot SC-1 treatment and the latter is removed by organic removal cleaning followed by dilute HF etching.

Inline FOUP Cleaner - The New Type FOUP Cleaner for the Next Generation

The existing methodology for Front Opening Unified Pod (FOUP) cleaning, storage, and transfer is inherently flawed in three areas: a) equipment layout, b) intra-process wait time, and c) human handling. In each area, improved solutions are suggested and a new approach is developed and named In-line FOUP Cleaner (IFC). IFC is a new, singular approach accomplished via total integration of multiple equipment types including sorter, FOUP cleaner, stocker, particle counter, and the FDC monitoring system. Utilizing the IFC approach, significant improvements have been documented with respect to all three areas of concern. Overall cost savings, as well as a side benefit of improved fume removal, are carefully observed. It appears to be an interesting approach to solving the problems associated with FOUP cleaning, storage, and transfer for the next generation semiconductor fab.

Removal of Fine Particle Using SAPS Technology and Functional Water

Space alternated phase shift (SAPS) megasonic technology incorporating with functional water, with dissolving gases H2 or N2, was applied to remove fine particle in wet cleaning processes of semiconductor manufacturing in this study. The performances of particle removal were investigated quantitatively by varying the parameters of functional water and megasonic energy. The optimized cleaning performance was further proved with significant yield improvement of mass production by comparison with other main cleaning technology.

The Effect of Various Process Induced Damages on Wet Etching Rate Difference

On increasing device integration, the implantation steps are newly introduced to fabricate high speed devices [1]. An ultra high dose implantation step of very shallow junction is mandatory to improve device characteristics. The implantation for dual poly-gate formation, which employs very high dose (more than 1e16 atoms/cm), causes lots of problems such as polymer residue and cleaning induced film loss, and etc [2-4]. Especially, the film etching rate precise control on ultra high does implanted surface during is extremely difficult, even though the wet etching amount is very critical to fabricate current device fabrication. Furthermore, it is reported that the film loss should be controlled to less than 0.5 Å during each cleaning [5]. In this study, the various etching rates, based on the amount of implantation dose, dopant species, and etching depth, will be studied in great detail.

The Dependence of Chemical Mechanical Polishing Residue Removal on Post-Cleaning Treatments

Introduction Defect-free surface preparation after a chemical mechanical polishing (CMP) is of most importance for a highly integrated device manufacturing. On surface, the requirement to remove the process induced defect is the main driving force on increasing device integration. It is reported that the multi-layer exposed surface have the issue for the CMP induced defect removal [1]. A wet cleaning treatment for all surfaces with oxide, nitride, and poly silicon exposed after CMP process, which should have a good particle removal capability without increasing oxide film loss, is proposed hereafter for a highly integrated device. The author focuses on the relationship between the process induced defect and a boronphosphorus doped silicate glass (BPSG) etched thickness during the post cleaning, which is a big issue how to minimize the thickness to perfectly remove the defect from the surface.

Development of a Integrated Dry/Wet Hybrid Cleaning System

With scaling of ULSI devices, the process temperatures are continuously lowered. The oxide films, which were deposited at low temperature, show fast etching rates during wet etching compared to high temperature films. Also, the etch rates differ largely from other film deposition conditions. In order to overcome these etch rate differences during surface preparation, dry cleaning processes had been introduced where the etch selectivity of the soft oxide films to the thermal oxide are very similar, regardless of the film deposition conditions and the deposition temperature.

Elimination of Watermark on Extremely High-Doped Poly-Silicon Surfaces Using HF-Vapor Cleaning

Introduction Advanced mobile and high performance device manufacturing requires the development of low power, high density and high speed DRAM devices that operate at low voltages. However, as threshold voltage (Vt) decreases, the potential for Short Channel Effect (SCE) increases within the buried channel (BC) pMOSFET. This issue has led to development of the dual-gate surface channel (SC) pMOSFET to increase the SCE margin. During the Dual Poly Gate (DPG) process, highly doped P+ polysilicon and N+ polysilicon surfaces are exposed in the clean process, which may cause watermark problems. To overcome the water-mark generation problem during wafer drying due to differences of wetting characteristics and contact angles between N+ polysilicon and P+ polysilicon surfaces following the clean prior to WSix deposition, we altered the conventional wet clean to an SC-1 last clean and dry followed by a single-wafer HF vapor clean.