Gholamreza Ardeshir

A novel architecture for low voltage-low power DLL-based frequency multipliers

New architecture for a DLL based frequency multiplier for wireless transceivers presents in this paper. This architecture has the advantages of occupying low area, low power, low voltage and low phase noise. Also good stability can be obtained in this design. This structure also can be used for generating big multiples of reference frequency. The proposed circuit can operate at a substantially low supply voltage. The circuit level and system level designs are presented. Also power consumption trade-offs are reported. Simulation results confirm the analytical predictions. The proposed DLL-based frequency multiplier is implemented in a 0.13um CMOS Technology.

A new fast-lock, low-jitter, and all-digital frequency synthesizer for DVB-T receivers

Lock time and convergence time are the most important challenges in delay-locked loops DLLs. In this paper we cover French very high frequency band with a novel all-digital fast-lock DLL-based frequency synthesizer. Because this new architecture uses a digital signal processing unit instead of using phase frequency detector, charge pump, and loop filter in conventional DLL, therefore, it shows better jitter performance, lock time, and convergence speed than previous related works. Optimization methods are used to make input and output signals of the proposed DLL in phase. The proposed architecture is designed to cover all channels of French very high frequency band by choosing number of delay cells in signal path. Simulation has been done for 22-27 delay cells, and fREF=16MHz, which can produce output frequency in range of 176-216MHz. Locking time is approximately 0.3µs, which is equal to five clock cycles of reference clock. All of the simulation results show superiority of the proposed structure. Copyright

Digital delay locked loop-based frequency synthesiser for Digital Video Broadcasting-Terrestrial receivers

In this study, the authors cover French very high frequency (VHF) band with a novel all-digital fast lock delayed looked loop (DLL)-based frequency synthesiser. Since this new architecture uses a digital signal processing unit instead of phase-frequency detector, charge pump and loop filter in conventional DLL therefore it shows better jitter performance, locktime and convergence speed. To obtain in-phase input and output signals in DLLs, optimisation methods are used in the proposed architecture. The proposed architecture is designed to cover channels of French VHF band by choosing number of delay cells in signal path. Simulation has been done for 22–27 delay cells and f REF = 16 MHz which can produce output frequency in range of 176–216 MHz. Locking time is approximately 0.5 μs which is equal to 8 clock cycles of reference clock. All of simulation results show superiority of the proposed structure.

Jitter of Delay-Locked Loops Due to PFD

In this paper, delay-locked loops (DLLs) jitter due to uncertainties in the phase frequency detector (PFD) is calculated. First, time-domain equations of the DLL are introduced. These equations are the key to obtaining a closed-form equation related to the jitter of DLL in presence of a noisy PFD. Jitter equations at the output of all stages are calculated theoretically. A DLL is designed in 0.18-μm CMOS technology to validate the obtained equations.

Analysis of Millimeter-Wave LC Oscillators Based on Two-Port Network Theory

In this brief, a cross-coupled oscillator is analyzed based on the two-port network theory and the

An analytical model with flexible accuracy for deep submicron DCVSL cells

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Design of Novel Testable and Diagnosable Phase-Frequency Detector

- parameter model for a transistor. Contrary to the previous works, the proposed analysis shows that LC cross-coupled oscillators have an additional and higher pure imaginary natural frequency at which the circuit cannot oscillate. The analysis investigates the sufficient condition at which the circuit is able to oscillate at this higher frequency. For the oscillation at the higher frequency mode, we propose adding an extra stage and making a three-stage ring oscillator. The equations obtained from this analysis indicate that the oscillation start-up condition depends on the oscillation frequency. Hence, increasing the speed of the oscillator does not satisfy the start-up condition of oscillators. Our analysis shows that the maximum frequency, in which the circuit stops oscillation in the ring oscillator, is higher than the cross-coupled oscillator and this maximum frequency is very close to the maximum frequency of the transistor.

Analysis of DLL Jitter due to Voltage-Controlled Delay Line

ABSTRACT Differential cascoded voltage switch logic (DCVSL) cells are among the best candidates of circuit designers for a wide range of applications due to advantages such as low input capacitance, high switching speed, small area and noise-immunity; nevertheless, a proper model has not yet been developed to analyse them. This paper analyses deep submicron DCVSL cells based on a flexible accuracy-simplicity trade-off including the following key features: (1) the model is capable of producing closed-form expressions with an acceptable accuracy; (2) model equations can be solved numerically to offer higher accuracy; (3) the short-circuit currents occurring in high-low/low-high transitions are accounted in analysis and (4) the changes in the operating modes of transistors during transitions together with an efficient submicron I-V model, which incorporates the most important non-ideal short-channel effects, are considered. The accuracy of the proposed model is validated in IBM 0.13 µm CMOS technology through comparisons with the accurate physically based BSIM3 model. The maximum error caused by analytical solutions is below 10%, while this amount is below 7% for numerical solutions.

All digital fast lock DLL-based frequency multiplier

This paper presents a novel fully testable and diagnosable structure for phase-frequency detectors. All procedures of converting the conventional PFD to the fully testable one are reported step by step. Also, the probability-based testability of proposed architecture is calculated. In addition, area considerations related to new fully testable PFD are introduced completely. At last, the proposed structure is designed in both system level and circuit level. The results of fully testable PFD in 0.13-μm CMOS technology are shown. Simulation results confirm the theoretical analysis.