Gi-Yong Song

Implementation of the super-systolic array for convolution

High-performance computation on a large array of cells has been an important feature of systolic array. To achieve even higher degree of concurrency, it is desirable to make cells of systolic array themselves systolic array as well. The architecture of systolic array with its cells consisting of another systolic array is to be called super-systolic array.In this paper we propose a scalable super-systolic array architecture which shows high-performance and can be adopted in the VLSI design including regular interconnection and functional primitives that are typical for a systolic architecture.

Super-Systolic Array for 2D Convolution

This paper proposes a bit-level super-systolic array for 2D convolution which needs 1-bit ports for each input or output sequence. In addition to the arrangement of delays for data flow synchrony, the super-systolic array in which the cell of systolic array is organized again as a systolic array is adopted to perform the bit-level data flow and operation on bit data. The derived super-systolic array for 2D convolution is synthesized using Synopsys design compiler based on Hynix 035 mum cell library and compared with conventional word-level systolic array for 2D convolution. The bit-level super-systolic design is very compact in that it needs only 1-bit ports for each I/O sequence instead of n-bit ports in word-level design besides the reduced area requirement without time penalty on the output

Simple hardware verification platform using SystemVerilog

A simplified hardware verification platform based on layered approach is implemented using SystemVerilog. SystemVerilog unifies several proven hardware design and verification languages in the form of extensions to Verilog HDL. The importance of a verification platform based on OOP technique is increasing for high-level functional verification. The proposed platform consists of components such as generator, driver, monitor and checker which are connected by channels. The structure and test procedure based on Teal/Truss are changed to be as simple as possible for those who are not familiar with OOP to understand and use the platform easily.

Case study : Co-simulation and co-emulation environments based on SystemC & SystemVerilog

The flow of universal system-level design methodology consists of system specification, system-level hardware/software partitioning, co-design, co-verification using virtual or physical prototype, and system integration. In this paper, hardware part and software part of a design are described with SystemVerilog and SystemC, respectively after hardware/software partitioning. The functional interaction between hardware part and software part of a design is verified through co-simulation in pure software domain, and then verified through co-emulation after implementation of hardware part onto a specific hardware emulator. Verilog PLI provides a mechanism for Verilog simulators to invoke C functions which are registered as system functions through a complex process of library registration. Communication between software part and hardware part running concurrently needs IPC. Low-level system functions of device driver or kernel are called from C functions which are registered into Verilog PLI library. In contrast to Verilog PLI, SystemVerilog DPI which is used in co-simulation of this paper provides a way to interface with C/C++ or any other foreign language. Functions and tasks registered to the shared library using DPI can be called out like native ones. ModelSim recently supports SystemC simulation with built-in compiler for SystemC design unit, so the co-simulation of SystemC design units and SystemVerilog modules is carried out as one simulation process on ModelSim. After co-simulation, co-emulation using an FPGA-based prototype board is carried out.

Implementation of a C-to-SystemC synthesizer prototype

A C-to-SystemC synthesizer which processes the input behavior according to high-level synthesis, and then transforms the synthesis result into SystemC code is implemented in this paper. In the synthesis process, the input behavioral description in C source code is scheduled using list scheduling algorithm and register allocation is performed using left-edge algorithm on the result of scheduling. In the SystemC process, the output from high-level synthesis process is transformed into SystemC code by combining it with SystemC features such as channels and ports. The operation of the C-to-SystemC synthesizer is validated through simulating the synthesis of elliptic wave filter in SystemC code.

SystemVerilog-based verification environment using SystemC custom hierarchical channel

A verification environment which is based on a constrained random layered testbench using SystemVerilog OOP is implemented in this paper to verify the functionality of DUT designed with synthesizable constructors of SystemVerilog. Although the uses of multiple inheritance in OOP appear to be less common than those of single inheritance, multiple inheritance is useful for creating class types that combine the properties of two or more class types. Because SystemVerilog OOP technique does not allow multiple inheritance, we adopt SystemC to design a component of verification environment which has multiple inheritance, and we combine SystemC design unit with the SystemVerilog-based layered testbench using SystemVerilog DPI and ModelSim macro. SystemVerilog DPI provides a way to interface with any other foreign language. Functions and tasks registered to shared library using DPI can be called out like native ones. ModelSim recently supports SystemC simulation with built-in compiler for SystemC design unit. In order to simulate SystemC design unit with ModelSim, the SystemC design unit should be modified using some macros provided by ModelSim. In this paper, FIFO channel frequently used in high-level communication is designed as a custom hierarchical channel which has three base classes; sc_channel, channel interface, and data payload interface. The low-layer components of the SystemVerilog-based layered testbench communicate with DUT using virtual interface, and other components can communicate with each other using FIFO channel. DUT in this paper includes BFM because most IPs designed for SoC are connected to a bus and controlled through the bus1.

Implementation of a hardware functional verification system using SystemC infrastructure

The implementation of a verification environment to check the behavior of a device-under-test using SystemC infrastructure is presented in this paper. SystemC is generally adopted in a system-level design methodology because of the capability of architectural model description and hardware/software co-design. The verification system implemented in this paper can explore design space using SystemC with a minor adaptation, and verify functional correctness of the progressively refined modules to RTL HDL. The infrastructure of the verification system uses intermediate user-defined channels as communication interface between variables of SystemC module and registers of Verilog module. SystemC modules of the verification system can be reused for other hardware component verification because of the object-oriented feature of SystemC. The functional verification of an UART is performed on the proposed verification system.

Design and verification of an application-specific PLD using VHDL and SystemVerilog

This paper presents a new application-specific PLD architecture which adopts a bit-level super-systolic array for application-specific arithmetic operation such as MAC. The proposed design offers a significant alternative view on programmable logic device. The bit-level super-systolic array whose cell contains another systolic array is ideal for newly proposed PLD architecture in terms of area efficiency and clock speed as it limits the routing requirement in the PLD to local interconnections between Logic Units and to global interconnections between Logic Modules. The maximum clock cycle is limited only by one AND gate and one full adder. Operations of convolution and FIR filter implemented on the proposed PLD are checked using a SystemVerilog-coded verification platform.

Case study: Functional verification of a reconfigurable systolic array using truss

This paper introduces our experience in verifying the operation of each systolic array before and after reconfiguration using Truss. Truss is an implementation of an open-source verification infrastructure based on layer approach. Reconfigurable systolic array for solving either single-source shortest path problem or 0–1 knapsack problem is chosen as a reconfigurable device-under-test. One systolic array can be reconfigured into the other and vice versa according to the problem. The functional verification is performed on a reconfigurable device-under-test using Truss configured to this specific hardware.1

Design of a reversible PLD architecture

Reversible gate is a circuit that has the same number of inputs and outputs satisfying one-to-one mapping between the vectors of input and output. So far several logic synthesis methods for reversible logic have been proposed, however, they are not able to synthesize a reversible function with input and output of arbitrary width in a constructive manner based on building blocks and interconnect. This paper proposes a new reversible PLD(programmable logic device) architecture that enables any reversible function to be implemented by cascading the building blocks, or logic units through interconnect, and fits well on arithmetic circuits in particular. Also, a new reversible gate, T2F gate, is suggested and adopted in the proposed reversible PLD architecture. Both reversible PLD and T2F gate offer significant alternative view on reversible logic synthesis.