Gianfranco Avitabile

A neural architecture for the parameter extraction of high frequency devices [MMICs]

A novel optimization technique for the parameter identification of microwave monolithic integrated circuits is presented. It is based on a hybrid neural network whose learning process convergence allows the validation of the circuit approximated lumped model. The main feature of such a learning process is that no external desired signal is required and the neural network can be considered of the unsupervised type. Furthermore, the neural network output represents the lumped circuit parameter estimation.

Distributed amplifier design for UWB positioning systems using the gm over id methodology

In this paper we exploit the gm over ID methodology to optimize the design of a four stage conventional Distributed Amplifier (DA) for an Ultra-Wide Band positioning system. The W/L ratio and the DC-biasing of the amplifiers transistors are determined according to the gm over ID methodology by using a series of lookup tables generated starting from the model of the devices. The DA was designed using the IHP 0.13 μm SiGe process and provides a 14 dB gain over a bandwidth of 10.6 GHz. The input/output return loss of the amplifier is lower than -17 dB over the entire bandwidth, with an average noise figure of 1.95 dB and a 26 mW DC-power consumption.

A 2-GS/s 0.35μm SiGe track-and-hold amplifier with 7-GHz analog bandwidth using a novel input buffer

In this paper a Track-and-Hold amplifier (THA), designed in a low cost 0.35μm SiGe 60GHz technology, suitable for SDR applications, is presented. With the implementation of a novel input buffer, the circuit shows a 3dB bandwidth of 7GHz and a distortion better than 50dB up to, about, that frequency during Track phase. Simulations show a THD better than 50dB up to a frequency of 5.77GHz at 2GS/s and a “reconstructed” 3dB full power bandwidth (FPBW) of 5.86GHz. The circuit draws about 220mA from 3.3V supply, considering all the sampling stage, the output buffer and clock driver.

A 2.5-GS/s 62dB THD SiGe Track-and-Hold Amplifier with feedthrough cancellation technique

In this paper a Track-and-Hold Amplifier (THA), designed in a low cost 0.35μm SiGe 60GHz technology is presented. Thanks to the joint action of a novel input buffer and a suppression feedthrough architecture, it is able to guarantee 62dB Total Harmonic Distortion(THD) up to a frequency of 2.2GHz with 0.9Vp-p differential input at a sampling rate (Fs) of 2.5GS/s. The THA core draws about 145mA from 3.5V supply.

New wideband Distributed Voltage Controlled Oscillator with a coarse-fine tuning

The modern telecommunication services require increasingly wide tuning bands and improved spectral purity in order to support the growing demand for high data rate in the new generation wireless standards. The resulting VCOs have to deal with a difficult trade-off between wide tuning bandwidth and phase-noise. The paper introduces a new VCO architecture with a double tuning control, the former coarse to select the band the latter fine to precisely tune the frequency. The VCO is organized in an innovative distributed arrangement. Experimental results validating the theory are reported and discussed

A novel high Q active inductor for millimeter wave applications

The paper introduces an active inductor implementation suitable for microwave and millimeter wave applications. The proposed circuit exhibits a quality factor in excess to 500 at 25 GHz with a current consumption of 1.2 mA @ 1.5V bias. A Monolithic implementation in PHEMT technology is reported and discussed.

Gm over ID design for UWB distributed amplifier

This paper presents the optimized design of a conventional four-stage distributed amplifier for Ultra-Wide Band applications (UWB). The design flow exploits the gm/ID methodology in order to optimize the size of the transistors to achieve the best tradeoff between gain, input/output matching, noise figure and power DC consumption. The circuit was designed using a 0.13 μm process from IHP Microelectronics, it exhibits a gain of 11 dB over the frequency range from 3.1 to 10.6 GHz and an average noise figure of 2.65 dB. The input/output return loss are lower than 16 dB and the amplifier dissipates only 26 mW with 1.2 V supply. Finally, the chip measures only 1.07 mm × 0.7 mm.

A high precision phase control unit for DDS-based PLLs for 2.4-GHz ISM band applications

This paper introduces the design and implementation of a new programmable phase control unit (PCU) topology for active phased array antennas. The array is based on a hybrid direct digital synthesizer (DDS) phase-lock-loop (PLL) approach. The PCU generates up to 1024 phase shift values programmable in the form of phase-offset words by either a microcontroller or a DSP. As a result a 360° phase shifting range can be scanned in 0.35° tuning steps, which correspond to a beam steering resolution smaller than about 0.5°. Experimental results obtained through the fabrication of a prototype validate the potential of the proposed architecture, and are in good agreement with both simulation and theoretical analysis. The phase shifter is designed and demonstrated across the 2.4-GHz industrial-scientific-medical (ISM) band.

A high bandwidth 11-bit 1.5GS/s track and hold amplifier in 0.25 µm SiGe BiCMOS

The paper describes a Track and Hold Amplifier suitable for high-speed and high resolution applications like Software Defined Radios. Thanks to the adopted techniques to maximize the resolution without reducing the sampling frequency, all the non idealities limiting the equivalent number of bits have been taken into account. In particular a novel technique to reduce the third harmonic distortion has been proposed and exploited. Post-layout simulations show that the performances are quite constant and the linearity is compatible with 11-bit (SFDR) at Fs= 1.5GS/s up to a frequency 1GHz.

A 11-bit Track and Hold Amplifier in 0.25 µm SiGe BiCMOS for RF sampling receivers

The paper describes a Track and Hold Amplifier (THA) suitable for RF sampling and Software Defined Radio receivers where high speed and high resolution are required. The reported THA is based on two main techniques: one for minimizing the differential droop rate and one for improving the HD3 in track mode. Measurements results show that the adopted solutions are both effective. In the desired input band around 1GHz, at the desired sub-sampling frequency (0.5GS/s) the THA provides a linearity compatible with 12-bit (Spurious Free Dynamic Range, SFDR). Moreover at the maximum achievable sampling frequency (1.5GS/s) the performances are quite constant and the resolution is compatible with 11-bit (SFDR) up to an input frequency of 1GHz.