Gianpaolo Prina

A trace-driven simulator for performance evaluation of cache-based multiprocessor systems

We describe a simulator which emulates the activity of a shared memory, common bus multiprocessor system with private caches. Both kernel and user program activities are considered, thus allowing an accurate analysis and evaluation of coherence protocol performance. The simulator can generate synthetic traces, based on a wide set of input parameters which specify processor, kernel and workload features. Other parameters allow us to detail the multiprocessor architecture for which the analysis has to be carried out. An actual-trace-driven simulation is possible, too, in order to evaluate the performance of a specific multiprocessor with respect to a given workload, if traces concerning this workload are available. In a separate section, we describe how actual traces can also be used to extract a set of input parameters for synthetic trace generation. Finally, we show how the simulator may be successfully employed to carry out a detailed performance analysis of a specific coherence protocol. >

Trace Factory: generating workloads for trace-driven simulation of shared-bus multiprocessors

A major concern with high-performance general-purpose workstations is to speed up the execution of commands, uniprocess applications, and multiprocess applications with coarse- to medium-grain parallelism. The authors have developed a methodology and a set of tools to generate traces for the performance evaluation of shared-bus, shared-memory multiprocessor systems. Trace Factory produces traces representing significant real workloads consisting of a flexible set of commands and uniprocess and multiprocess user applications. The authors evaluate its accuracy and show how it can be used to evaluate and compare the performance of five coherence protocols.

A workload generation environment for trace-driven simulation of shared-bus multiprocessors

We describe an environment to produce traces representing significant workloads for a shared-bus shared-memory multiprocessor used as a general-purpose multitasking machine, where each processor can include multithread facilities. By means of an exclusively software approach, the environment produces traces that include both user and kernel references, starting from source traces containing only user references. The process scheduling and the virtual-to-physical address translation are simulated in detail, whereas a stochastic model is provided for the generation of the kernel reference stream. The paper includes a section describing the generation of three different workloads used to evaluate the performance of a shared-bus shared-memory multiprocessor.

A hybrid approach to trace generation for performance evaluation of shared-bus multiprocessors

This paper describes a hybrid methodology (based on both actual and synthetic reference streams) to produce traces representing significant complete workloads. By means of a software approach, we generate traces that include both user and kernel references starting from source traces containing only user references. We consider the aspects of kernel that have a deeper impact on the multiprocessor performance by (i) simulating the process scheduling and the virtual-to-physical address translation, and (ii) stochastically modeling the kernel reference stream. The target system of our study is a shared-bus shared-memory multiprocessor used as a general-purpose machine with a multitasking operating system.

Cache memory design for embedded systems based on program locality analysis

Cache memory design in embedded systems can take advantage from the analysis of the software that runs on that system, which usually remains the same for its whole life. Programs can be characterized, in respect of the memory hierarchy, using locality analysis. We propose an environment which permits one to analyze the locality of a program and the effects on the target system performance. The student can thus figure out the best tradeoff between costs and performance for cache memory and timings, exploring different system configurations. A fully graphical interface permits one to observe the program behavior from many points of view: locality surface, working set evolution, and performance metrics. The tool is currently used as a teaching tool at our University and it is distributed as part of a commercial development environment for embedded systems.

An educational environment for program behavior analysis and cache memory design

The authors present an educational software package (Csim) used as a teaching tool to analyze the structure and behavior of a cache memory and to help the student in the design of cache memories for embedded systems. By means of an integrated software development environment, the user can create a program and explore its behavior (locality analysis). The student can observe the cache actions needed for a memory operation and evaluate the cache performance as a function of the configuration parameters. Finally, the parametric-evaluation graphical tools help in the actual design of an embedded system, in order to find the cache and memory configuration which provides the best balance between cost and performance.

Reducing coherence-related overhead in multiprocessor systems

The coherence problem is one of the critical issues designers have to cope with when they apply caching techniques to multiprocessor systems. The copies which most affect consistency are the shared ones, i.e. copies of memory blocks accessed by concurrent processes in a multiprogramming environment; nevertheless, a private data block of a process may become resident in more than one cache-and need to be treated as shared (useless shared copy) with respect to coherence-related operations-as a consequence of the migration of the owner process. These copies reduce the global performance of the system, since they involve a useless (time consuming) transaction on the shared bus on each write operation, to maintain consistency of all remote copies. In the paper, we introduce a hardware solution which can be successfully employed with any snooping protocol to eliminate useless shared copies. Finally, we show how this technique can be applied to a specific coherence protocol, in order to improve global system performance.<<ETX>>