Gilbert C. Sih

A compile-time scheduling heuristic for interconnection-constrained heterogeneous processor architectures

The authors present a compile-time scheduling heuristic called dynamic level scheduling, which accounts for interprocessor communication overhead when mapping precedence-constrained, communicating tasks onto heterogeneous processor architectures with limited or possibly irregular interconnection structures. This technique uses dynamically-changing priorities to match tasks with processors at each step, and schedules over both spatial and temporal dimensions to eliminate shared resource contention. This method is fast, flexible, widely targetable, and displays promising performance. >

Declustering: a new multiprocessor scheduling technique

The authors present a new compile-time scheduling heuristic called declustering, which schedules acyclic precedence graphs that fit the synchronous data flow (SDF) model onto multiprocessor architectures. This technique accounts for interprocessor communication (IPC) overheads and considers interconnection constraints in the architecture so that shared resource contention can be avoided. The algorithm initially invokes a new clustering method that uses graph-analysis techniques to isolate parallelism instances. When constructing an initial set of clusters, this procedure explicitly addresses the tradeoff between exploiting parallelism and incurring communication cost. By hierarchically combining these clusters and then systematically decomposing this hierarchy, the declustering method exposes parallelism instances in order of importance and attains a cluster granularity that fits the characteristics of the architecture. It is shown that declustering retains the clustering advantage of avoiding IPC, yet overcomes the inflexibility associated with traditional clustering approaches. >

Gabriel: a design environment for DSP

Gabriel, a second-generation digital signal-processing (DSP) design environment, is described. The Gabriel experimental signal-processing software performs non-real-time algorithm simulations and code synthesis for real-time hardware based on programmable DSPs. Gabriel eases code development for architectures that are not easy targets for conventional compilers. The model of compilation used by Gabriel is discussed at length. Modification of the model to run in real time, target architectures, and scheduling are examined.<<ETX>>

Dynamic-level scheduling for heterogeneous processor networks

Dynamic-level scheduling is an effective compile-time scheduling technique which accounts for interprocessor communication overhead when mapping precedence-constrained, communicating tasks onto arbitrarily interconnected processor networks. Scheduling and routing are performed simultaneously to account for limited interconnections between processors, and communications are scheduled along with computations to eliminate shared-resource contention. The paper extends the dynamic-level scheduling methodology to encompass heterogeneous processing environments, and presents two techniques designed to enhance scheduling performance: forward/backward scheduling, and precedence constraint appendage.<<ETX>>