Giorgio Allegato

Hermetic wafer level packaging of MEMS components using through silicon via and wafer to wafer bonding technologies

This paper presents the fabrication steps of a MEMS package based on silicon interposer wafers with copper filled TSVs and bonded cap wafers for hermetic sealing of resonator components. All processes were performed at 200 mm wafer level. For interposer fabrication a standard process flow including silicon blind hole etching, isolation, copper filling, wafer front side redistribution, support wafer bonding, wafer thinning, and TSV backside reveal was applied. As interposer backside metallization, appropriate I/O terminals and seal ring structures were deposited by semi-additive Au and Au+Sn electro plating. Following, getter material was deposited onto the interposer wafers which were 90 μm thick and still mounted onto carrier wafers. Subsequently, the I/O terminal pads of the interposer were stud bumped and finally more than 5000 quartz resonator components were assembled onto each interposer wafer by Au-Au direct metal bonding. The cap wafer was equipped with 200 μm deep dry etched cavities and electro plated Au seal rings around them. Finally, both cap and interposer wafers were bonded together using a wafer to wafer bonder and an adapted AuSn soldering process scheme. In a last step, the carrier wafer was removed from the former front side of the interposer wafer and wafer level testing was performed. From a total of 4824 tested devices we found that more than 75 % were sealed properly under vacuum. The getter appears to be effective leading to ~0.1 mbar equivalent air pressure and cavities without getter appear to reach residual air pressure between 1-2 mbar. The used fabrication processes and final results will be discussed detailed in this manuscript.

Application of TSV integration and wafer bonding technologies for hermetic wafer level packaging of MEMS components for miniaturized timing devices

The paper presents different approaches for hermetic wafer level packaging of oscillator components like quartz crystals or silicon resonators. The proposed concepts involve technologies like TSV formation into passive or active silicon wafers, formation of proper bond frames on interposer, ASIC or cap wafers as well as hermetic bonding using AuSn soldering either in wafer to wafer style or with reconfigured components on a carrier wafer.

Wafer level packaging of MEMS and 3D integration with CMOS for fabrication of timing microsystems

The following paper gives an insight on the packaging concepts and fabrication processes used to ultimately manufacture a timing module at wafer scale. The packaging of the timing module consists in the integration of an ASIC together with a Quartz-based or Twin-Silicon resonator MEMS which require to be hermetically sealed under vacuum for proper function. The 3D-integration enables a significant miniaturization of the complete system. Subsequently a BAW (Bulk Acoustic Wave) resonator can be further associated over the quartz resonator to form a MEMS-based freely programmable oscillator for stable clock generation, covering a large frequency range between 1 and 50 MHz. The principal fabrication processes include the implementation of Through-Silicon Vias (TSV) in active CMOS wafers, temporary wafer bonding for thin wafer handling and wafer bonding for metallic sealing under vacuum and formation of electrical interconnects. The components were packaged by chip to wafer assembly onto active CMOS wafers with TSVs and subsequent wafer to wafer bonding with a corresponding cavity cap wafer for vacuum encapsulation. All processes have been developed and performed at 200 mm industrial wafer scale.

A three-scale approach to the numerical simulation of metallic bonding for MEMS packaging.

Abstract In this work we present a numerical, multi-scale approach to estimate the strength of a wafer-to-wafer metallic thermo-compression bonding. Following a top-down approach, the mechanical problem is handled at three different length scales. Taking into account control variables such as temperature, overall applied force over the wafer and contact surface roughness, it is shown that the proposed approach is able to provide an estimate of the sealing properties, especially in terms of bonding strength.