Giovanni B. Vece

Performance analysis of different arbitration algorithms of the AMBA AHB bus

Bus performances are extremely important in a platform-based design. System Level analysis of bus performances gives important information for the analysis and choice between different architectures driven by functional, timing and power constraints of the System-on-Chip. This paper presents the effect of different arbitration algorithms and bus usage methodologies on the bus AMBA AHB performances in terms of effective throughput and power dissipation. SystemC and VHDL models have been developed and simulations have been performed.

PK tool 2.0: a SystemC environment for high level power estimation

Power dissipation has become one of the main constraints during the design of complex integrated circuits in the recent years, due to the steady increasing of integration level and operating clock frequency. Power consumption is a major design issue and thus it requires the availability of effective tools for power estimation and optimization. Moreover, it is known that power analysis and optimization during the early design phases, starting from system level descriptions, can lead to large power savings. In this paper we present PK tool 2.0, an effective object-oriented library for SystemC 2.0.1, which allows the easy introduction of a power model in the executable specification of a complex design.

Transaction-level power analysis of VLSI digital systems

The increasing complexity of VLSI digital systems has dramatically supported system-level representations in modeling and design activities. This evolution makes often necessary a compliant rearrangement of the modalities followed in validation and analysis tasks, as in the case of power performances estimation.Nowadays, transaction-level paradigms are having a wider and wider consideration in the research on electronic system-level design techniques. With regard to the available modeling resources, the most relevant framework is probably the transaction-level extension of the SystemC language (SystemC/TLM), which therefore represents the best platform for defining transaction-level design techniques.In this paper we present a macro-modeling power estimation methodology valid for SystemC/TLM prototypes and of general applicability. The present discussion illustrates the implementation modalities of the proposed approach, verifying its effectiveness through a comparison with RTL estimation techniques. The paper deals with power analysis on transaction-level models of complex digital systems.We propose an estimation methodology strictly based on the modeling constructs of SystemC/TLM and of general applicability.We consider the comparison with RTL power estimation techniques on several design aspects: estimation accuracy, simulation time and modeling effort,The experimental results show the design advantages of the proposed methodology with respect to RTL estimation techniques.

Power analysis methodology and library in SystemC

Power dissipation has become one of the main constraints during the design of complex integrated circuits in the recent years, due to the steady increasing of integration level and operating clock frequency. Power consumption is a major design issue and thus it requires the availability of effective tools for power estimation and optimization. Moreover, it is known that power analysis and optimization during the early design phases, starting from the system level, can lead to large power savings. In this paper we present Power-Kernel, an efficient object-oriented library for SystemC 2.0, which allows the easy introduction of a power model in the executable specification of a complex design.

A new test structure for short and long distance mismatch characterization of submicron MOS transistors

A new test structure for the characterization of statistical variations of the parameters of submicron MOS devices is presented in this work. The structure has been designed for the estimation of mismatch parameters as a function of the device dimensions and positions in the die. Low area consumption and a reduced measurement time required for the complete mismatch characterization are the main objective of the design. The test structure consisting of about 6000 MOSFETs has been used for mismatch characterization of a 0.18 /spl mu/m CMOS technology.

Mixed signal SystemC modelling of a SoC architecture with Dynamic Voltage Scaling

Dynamic Voltage Scaling is a technique that reduces supply voltage and clock frequency, depending on system workload, with the aim of reducing power dissipation. This works is devoted to the modelling and integration in the same system level simulation environment of the analog DC-DC converter for Dynamic Voltage Scaling, the Dynamic Power Management and a test System on Chip with three Masters and two Slaves connected to the AMBA AHB bus. The DC-DC converter is described with a detail such that it is possible to verify the effect of the transient during the change of supply voltage on the performance of the DVS algorithm. SystemC and its extension SystemC-WMS have been used as description languages in which a system level description of the dynamic supply management coexists with the analog switching power converter and its control.

System level design and power analysis of architectures for SATD calculus in the H.264/AVC

The new generation of video coding standards (H.264/MPEG Advanced Video Codec) addresses the requirements of a network-friendly and scalable video representation, and increasing by a factor of two the compression efficiency of the current technology. The H.264 uses the SATD metric for the calculus of the prediction error. The SATD procedure may be called about 1 million times during the visualization of a 352x288 pixel video sequence of 10 seconds. Therefore the accurate design of a dedicated hardware for the SATD is relevant in the performance of the complete codec. This paper presents four architectures described in SystemC for the VLSI implementation of the calculus of the SATD metric. The performances of the architectures in terms of signal to noise ratio and power dissipation have been evaluated using a new SystemC library developed by the authors for the estimation of power consumption in a SystemC description of the architecture. Comparisons have been performed for different values of the number of bits of the internal representation for the four architectures. Four standard video sequences (Akiyo, Stefan, Mobile&calendar, Container) have been used to test the performance of the architectures.

Energy estimation in SystemC with Powersim

Abstract This paper presents a methodology to estimate the dissipation of energy in hardware, at any level of abstraction, with Powersim. Powersim is a C++ class library aimed to the calculation of energy dissipation of hardware described in SystemC. To this end C++ operators are monitored and a different energy model is used for each data type. Energy models are functions of operator inputs, constant parameters and variables, like supply voltage. The main advantage of this approach is that energy estimation does not require any change in the source code describing the hardware. As application examples, the computational complexity of a JPEG encoder, implemented in a FPGA, and a FIR filter, implemented in a microcontroller, are presented.

Protocol-level noise analysis of networked systems based on simulation/analytical approach

Reliability and noise tolerance represent important requirements for digital networked systems, especially in critical working conditions. These issues mostly concern the communication tasks between the network nodes, which are usually implemented on the basis of formal protocol rules. A challenging target for a reliability analysis is to provide comprehensive evaluations and acceptably accurate results. However, the current complexity of many network applications entails relevant limitations to this possibility. In this paper we present a novel system-level methodology for noise analysis of digital networked systems. In our research we have defined a simulation/analytical approach entirely based on the protocol specifications and capable to address a fast and comprehensive study of the reliability properties. The proposed methodology is illustrated through a case study on the MOST 150 protocol, which is currently used to realize multimedia networks in automotive contexts.

Power Analysis of Embedded Systems

The estimation of power dissipation at system level allows to consider the specification of power dissipation in the first phases of the design process. This paper describes the main features and components of the PKtool simulation environment, a power estimation tool recently made available and easily integrable in a SystemC/C++ workflow. The final part of the chapter reports an example where PKtool has been used to evaluate the power performances of the Bluetooth communication protocol.