Giovanni Staino

Low bit rate image compression core for onboard space applications

This paper presents low-cost, purpose optimized discrete wavelet transform-based image compressors for future spacecrafts and microsatellites. The hardware solution proposed here exploits a modified set partitioning in hierarchical trees algorithm and ensures that appropriate reconstructed image qualities can be achieved also for compression ratios over 100:1. Several implementations are presented varying the parallelism level and the tile size. Obtained results demonstrate that, using a parallel implementation operating on a 64 /spl times/ 64 size tile, a maximum data rate of about 18 Mpixels/s can be sustained. In this case, only 4500 slices and 24 BlockRAMs of a XILINX Virtex II device are required.

A low-power sub-nanosecond standard-cells based adder

This paper presents a new standard-cells based low-power subnanosecond 64-bit adder. For the first time, in the proposed circuit, a hybrid quaternary carry-look-ahead carry-skip tree is exploited to quickly compute carries into appropriate positions. Moreover, sum units organized as carry-increment blocks are used. When realized with the standard-cell libraries of the ST 0.18 /spl mu/m 1.8 V CMOS technology, the new adder exhibits a computational delay of just 980 ps, an average power dissipation of 27 mW at 500 MHz and a silicon area occupancy of about 0.015 mm/sup 2/.

Efficient implementation of cellular algorithms on reconfigurable hardware

Reconfigurable architectures represent an innovative approach to the computer system design paradigm, which tries to cope with a problem of inefficiency of conventional computing systems, due to their general purpose nature. On the other hand, cellular automata are attractive computing models due to their fine grain parallelism, simple computational structures and local communication patterns. The inherently parallel cellular automata model is well suited to be implemented on reconfigurable hardware architectures such as field programmable gate arrays (FPGA) that can provide significant speedup. This paper describes the CAREM system that provides an efficient implementation of cellular automata algorithms on FPGA systems exploiting their reconfigurable features for executing different cellular automata rules. Its application to an image processing application and a forest fire simulation are presented and discussed. Performance evaluation and comparison with different implementations of cellular automata are presented.

Dynamic power of CMOS gates driving lossy transmission lines

The dynamic power consumption of a complementary metal-oxide-semiconductor (CMOS) gate driving a resistance-inductance-capacitance (RLC) transmission line is investigated in this paper. The closed-form solution for the dynamic power has been carried out by a simple time domain model for input impedance of a lossy transmission line, specifically developed to be used in conjunction with MOS macromodels. The proposed solution agrees with circuit simulations within 1% error for a wide range of line parameters, and it demonstrates how power dissipation localized in the wire resistance may be a significant aliquot of the global power consumption.

VLSI implementation of a fully static CMOS 56-bit self-timed adder using overlapped execution circuits

Self-timed adders are widely used since they compute in mean time. Traditionally, in order to achieve very high-speed performance they are realized using dynamic CMOS logic (Domino, DCVSL). However, recent works have demonstrated that efficient self-timed adders can also be realized using fully static CMOS circuits. In this paper, a new high-performance fully static 56-bit self-timed adder is presented. The proposed VLSI implementation uses overlapped execution circuits, which perform their computation by exploiting the initialization time elapsing between two consecutive operations. The new adder realized with AMS 0.6 /spl mu/m CMOS standard-cells shows an average addition time of /spl sim/3.3 ns, requires /spl sim/900000 /spl mu/m/sup 2/ of silicon area and consumes a maximum power of /spl sim/660 mW @300 MHz.

Quad-Port Memory Blocks in Radiation-Tolerant FPGAs: An Application for Image Processing Systems

This paper presents a novel memory architecture for implementing quad port memories in radiation tolerant FPGAs. The hardware solution proposed here uses only dual port memories and ensures that appropriate memory speed can be achieved while working as quad port memory. Efficient memory architecture has been used to transform dual port memory into quad port memory without using any redundant memory. The Discrete Wavelet transform has been effectively implemented using the proposed architecture on the Actel RTAX FPGA.

Parallel Multipliers using 3-Bit-Scan without Overlapping Bits

This paper presents a novel high-speed parallel multiplier based on 3-bit-scan without overlapping bits. The proposed multiplier is able to elaborate both signed and unsigned operands and it is suitable for both full-custom and standard-cells based VLSI implementations. When realized using the ST 90 nm CMOS standard-cells library, the 8x8 version of the novel multiplier exhibits a worst-case delay of only 0.93 ns and dissipates ~27 uW/MHz.

Design and Implementation of a 90nm Low bit-rate Image Compression Core

This paper presents a low-cost, high throughput discrete wavelet transform-based image compressor. The hardware solution proposed here exploits a modified set partitioning in hierarchical trees (SPIHT) algorithm and ensures that appropriate reconstructed image qualities can be achieved also for compression ratios over 100:1. Obtained results demonstrate that a maximum data rate of about 23 Mpixels/s can be sustained on a 64x64 size tile. In 90 nm technology, the required area is only 1.77 mm2. To obtain higher performance, multiples cores can be used in a parallel implementation.