Giovanny Sanchez

An efficient hardware implementation of a novel unary Spiking Neural Network multiplier with variable dendritic delays

We propose a novel unary spiking circuit for a serial multiplier with variable dendritic delays. Serial multipliers commonly use the soma model for the arithmetic operation. The structure of the serial multiplier and the efficient implementation of the dendritic delays on customized neuromorphic hardware are the major contributions of this work. The design of the multiplier was inspired by the biological processes of dendrites, which use feedback connections and dendritic growth to synchronize the neural processing performed by the soma. The multiplier eliminates complex rules by adopting the soma model with dendritic connectivity configurations, increasing the processing speed compared with previously reported solutions based on Spiking Neural Networks.

AER-SRT: Scalable spike distribution by means of synchronous serial ring topology address event representation

Abstract Given the massive number of interconnects in Spiking Neural Networks (SNNs), distributing spikes effciently becomes a critical issue for the efficient hardware emulation of large-scale SNNs. In this work, the AER-SRT (Address Event Representation over Synchronous Serial Ring Topology) architecture for spike transmission is proposed. AER-SRT is a light, easily scalable, packet-based solution implemented with high-speed serial link for multi-chip SNN communication. The channel uses a unidirectional, point-to-point connection between nodes, which provides a high transmission speed. Events (spikes) are distributed among all the nodes in a ring-topology pipeline fashion and the synchronous AER guarantees a collision-free scheme. The fast speed and efficient channel usage limits the spike distribution time to values that allow real-time operation for network sizes that can be calculated with simple design equations. Also, in the proposed communication protocol there is no specific or master node, so new nodes can be added to the ring by simply modifying two configuration parameters. As a proof of concept, a prototype of the architecture has been implemented and tested on FPGA development boards.Given the massive number of interconnects in Spiking Neural Networks (SNNs), distributing spikes effciently becomes a critical issue for the efficient hardware emulation of large-scale SNNs. In this work, the AER-SRT (Address Event Representation over Synchronous Serial Ring Topology) architecture for spike transmission is proposed. AER-SRT is a light, easily scalable, packet-based solution implemented with high-speed serial link for multi-chip SNN communication. The channel uses a unidirectional, point-to-point connection between nodes, which provides a high transmission speed. Events (spikes) are distributed among all the nodes in a ring-topology pipeline fashion and the synchronous AER guarantees a collision-free scheme. The fast speed and efficient channel usage limits the spike distribution time to values that allow real-time operation for network sizes that can be calculated with simple design equations. Also, in the proposed communication protocol there is no specific or master node, so new nodes can be added to the ring by simply modifying two configuration parameters. As a proof of concept, a prototype of the architecture has been implemented and tested on FPGA development boards

A novel parallel multiplier using spiking neural P systems with dendritic delays

High performance spiking neural multiplier.Parallel input data processing in SN P systems.Scalable parallel architecture based on SN P systems. In the last 10 years, there has been a considerable increase in the number of studies on the development of multiplier circuits based on spiking neural P systems with the aim of taking advantage of their intrinsic distributed parallel computing characteristics. Nevertheless, these efforts have had difficulties in adequately exploiting parallel data processing because they are designed to process the input data using a sequential protocol and thus suffer from the resulting increase in processing time. This paper develops a novel parallel multiplier that is based on spiking neural P systems and is capable of multiplying two natural numbers with many digits in parallel. The proposed method employs the divide and conquer strategy (i.e., segmenting the numbers into units, tens, hundreds, thousands, etc.), to optimize the processing time of the arithmetic operations, and every two units are treated by a single neuron that can calculate up to 9 9 sequentially. The use of one neuron to perform a sequential multiplication represents the best improvement in terms of the number of neurons that has been reported to date.

Spike-based compact digital neuromorphic architecture for efficient implementation of high order FIR filters

Finite impulse response (FIR) filters have been widely used in many digital signal processing applications because of their interesting properties such as phase linearity, bounded-input-bounded-output (BIBO) stability and easy implementation. However, the implementation of high order filters requires many multipliers. Several authors have proposed new methods such as multiple constant multiplication (MCM), distributed arithmetic (DA) and signed-powers-of-two (SPT) to avoid the use of multipliers by using the minimum number of registers. Nevertheless, the implementation of these strategies generates critical paths that limit their performance. In this work, we propose a compact hardware architecture to compute FIR filters at high processing speeds using new parallel neural multipliers. The scalability of the system enables the construction of many neural multiplier units for higher order FIR filters. To validate the proposal, the hardware architecture was implemented on the Kintex-7 field programmable gate array (FPGA) development kit. The results demonstrate that this new approach can be interfaced with the conventional binary systems to improve advanced signal processing applications such as high quality media contents, wireless communication and biomedical systems.

Spike-based analog-digital neuromorphic information processing system for sensor applications

A spiking-neuron-based system that combines analog and digital multi-processor implementations for the bio-inspired processing of sensors is reported. This combination allows creating a powerful bio-inspired multiple-input sensor processing system for environment perception applications. The analog front-end encodes the input signal in a signed spike representation, which is further processed by means of a digital Spiking Neural Network (SNN) on a Single-Instruction Multiple-Data (SIMD) multiprocessor. The spike distribution for both systems is based on Address-Event Representation (AER) scheme, asynchronous for the Analog Pre-Processor (APP) and synchronous for the Digital Multi-Processor (DMP), synchronized by means of an AER transceiver. A proof-of-concept application of the system being able to process sensory information has been demonstrated. The system utilizes 30-neurons emulated by the DMP to process spike-encoded information provided by its analog counterpart, enabling the feature extraction of the input signal. The frequency detection capability of the system is experimentally reported.

Performance evaluation and scaling of a multiprocessor architecture emulating complex SNN algorithms

The performance analysis of an efficient multiprocessor architecture that allows accelerating the emulation of large-scale Spiking Neural Networks (SNNs) is reported. After describing the architecture and the complex SNN algorithm mapping, the performance study demonstrates that the system can emulate up to 10,000 300-synapse neurons in real time at 64 MHz with conventional FPGAs. Important improvements can be achieved by using advanced technology and increased clock rate or by means of simple architecture modifications. The architecture is flexible enough to be efficiently applied to any SNN model in general.

A compact divisor based on SN P systems along with dendritic behavior

The Spiking Neural P (SN P) system is defined as a type of parallel computing mechanism bio-inspired by the behavior of the soma. Several authors have been employing these systems in order to create efficient arithmetic divisor circuits exploiting at maximum their intrinsic parallel processing. However, the current neural divisors expend a large amount of neurons with complex spiking rules to synchronize the input information to be processed by the soma. This work proposes a compact neural divisor that uses eight neurons and two type spiking rules per neuron. In addition, the proposed circuit includes the dendrites behavior as feedback connections, dendritic delays, reduction in the dendrite length and dendritic pruning into the conventional SN P systems in order to simplify the synchronization of the neural processing carried out by the soma. The results show that the proposed neural divisor can be implemented in embedded neuromorphic circuits. This, potentially allows its use in portable applications such as vision processing systems for mobile robots and cryptographic systems for mobile communication devices.

AER-SRT

Abstract Given the massive number of interconnects in Spiking Neural Networks (SNNs), distributing spikes effciently becomes a critical issue for the efficient hardware emulation of large-scale SNNs. In this work, the AER-SRT (Address Event Representation over Synchronous Serial Ring Topology) architecture for spike transmission is proposed. AER-SRT is a light, easily scalable, packet-based solution implemented with high-speed serial link for multi-chip SNN communication. The channel uses a unidirectional, point-to-point connection between nodes, which provides a high transmission speed. Events (spikes) are distributed among all the nodes in a ring-topology pipeline fashion and the synchronous AER guarantees a collision-free scheme. The fast speed and efficient channel usage limits the spike distribution time to values that allow real-time operation for network sizes that can be calculated with simple design equations. Also, in the proposed communication protocol there is no specific or master node, so new nodes can be added to the ring by simply modifying two configuration parameters. As a proof of concept, a prototype of the architecture has been implemented and tested on FPGA development boards.Given the massive number of interconnects in Spiking Neural Networks (SNNs), distributing spikes effciently becomes a critical issue for the efficient hardware emulation of large-scale SNNs. In this work, the AER-SRT (Address Event Representation over Synchronous Serial Ring Topology) architecture for spike transmission is proposed. AER-SRT is a light, easily scalable, packet-based solution implemented with high-speed serial link for multi-chip SNN communication. The channel uses a unidirectional, point-to-point connection between nodes, which provides a high transmission speed. Events (spikes) are distributed among all the nodes in a ring-topology pipeline fashion and the synchronous AER guarantees a collision-free scheme. The fast speed and efficient channel usage limits the spike distribution time to values that allow real-time operation for network sizes that can be calculated with simple design equations. Also, in the proposed communication protocol there is no specific or master node, so new nodes can be added to the ring by simply modifying two configuration parameters. As a proof of concept, a prototype of the architecture has been implemented and tested on FPGA development boards

A new scalable parallel adder based on spiking neural P systems, dendritic behavior, rules on the synapses and astrocyte-like control to compute multiple signed numbers

Abstract This brief presents a scalable parallel neural adder circuit based on spiking neural P systems along with dendritic delays, dendritic feedback, rules on the synapses and astrocyte-like control to create a compact and highly scalable adder circuit. The proposed neural adder circuit adds multiple signed numbers either with few digits or with large number of digits in parallel employing a reduced number of neurons/synapses with simple and homogeneous spiking rules. The proposed neural adder was implemented in a DE0-Nano board (Altera Cyclone IV FPGA) to validate its performance. The results show that its implementation on a low-area low-cost FPGA requires small amount of circuitry. This potentially allows the development of highly parallel architectures that can be used in advanced applications, such as portable mobile robots, mobile devices, image and vision processing, among others.

SNAVA—A real-time multi-FPGA multi-model spiking neural network simulation architecture

Spiking Neural Networks (SNN) for Versatile Applications (SNAVA) simulation platform is a scalable and programmable parallel architecture that supports real-time, large-scale, multi-model SNN computation. This parallel architecture is implemented in modern Field-Programmable Gate Arrays (FPGAs) devices to provide high performance execution and flexibility to support large-scale SNN models. Flexibility is defined in terms of programmability, which allows easy synapse and neuron implementation. This has been achieved by using a special-purpose Processing Elements (PEs) for computing SNNs, and analyzing and customizing the instruction set according to the processing needs to achieve maximum performance with minimum resources. The parallel architecture is interfaced with customized Graphical User Interfaces (GUIs) to configure the SNNs connectivity, to compile the neuron-synapse model and to monitor SNNs activity. Our contribution intends to provide a tool that allows to prototype SNNs faster than on CPU/GPU architectures but significantly cheaper than fabricating a customized neuromorphic chip. This could be potentially valuable to the computational neuroscience and neuromorphic engineering communities.