Giulio Casagrande

Non-Volatile Memory

An electrically programmable and erasable non-volatile semiconductor memory such as a flash memory is designed into a configuration in which, when a cutoff of the power supply occurs in the course of a write or erase operation carried out on a memory cell employed in the non-volatile semiconductor memory, the operation currently being executed is discontinued and a write-back operation is carried out to change a threshold voltage of the memory cell in the reversed direction. In addition, the configuration also allows the number of charge-pump stages in an internal power-supply configuration to be changed in accordance with the level of a power-supply voltage so as to make the write-back operation correctly executable. As a result, no memory cells are put in deplete state even in the event of a power-supply cutoff in the course of a write or erase operation.

4-Mb MOSFET-selected phase-change memory experimental chip

This paper presents a 4-Mb phase-change memory experimental chip using an MOS transistor as a cell selector. A cascode bit-line biasing scheme allows read and write voltages to be fed to the storage element with adequate accuracy. The chip was integrated with 3-V 0.18-/spl mu/m CMOS technology and experimentally evaluated. A read access time of 45 ns was measured together with a write throughput of 5 MB/s, which represents an improved performance as compared to present NOR Flash memories. Cell current distributions on the 4-Mb array proved chip functionality and a good working window, thus demonstrating the feasibility of a stand-alone phase-change memory with standard CMOS fabrication process.

An 8Mb demonstrator for high-density 1.8V Phase-Change Memories

An 8Mb Non-Volatile Memory Demonstrator incorporating a novel 0.32 /spl mu/m/sup 2/ Phase-Change Memory (PCM) cell using a Bipolar Junction Transistor (BJT) as selector and integrated into a 3V 0.18 /spl mu/m CMOS technology is presented. Realistically large 4Mb tiles with a voltage regulation scheme that allows fast bitline precharge and sense are proposed. An innovative approach that minimizes the array leakage has been used to verify the feasibility of high-density PCM memories with improved Read/Write performance compared to Flash. Finally, cells distributions and first endurance measurements demonstrate the chip functionality and a good working window.

A Multi-Level-Cell Bipolar-Selected Phase-Change Memory

Phase-change memory (PCM) is becoming widely recognized as the most likely candidate to unify the many memory technologies that exist today (Lee, et al., 2007). The combination of non-volatile attributes of flash, RAM-like bit-alterability, and fast reads and writes position PCM to enable changes in the memory subsystems of cellular phones, PCs and countless embedded and consumer electronics applications. This designs multi-level cell (MLC) capabilities combined with long- term scalability reduce PCM costs as only realized before by hard disk drives. MLC technology is challenged with fitting more cell states (4 in the case of 2 bit per cell), along with distribution spreads due to process, design, and environmental variations, within a limited window. We describe a 256Mb MLC test-chip in a 90nm micro-trench (mutrench) PCM technology, and MLC endurance results from an 8Mb 0.18mum PCM test-chip with the same trench cell structure. A program algorithm achieving tightly placed inner states and experimental results illustrating distinct current distributions are presented to demonstrate MLC capability.

SET and RESET pulse characterization in BJT-selected phase-change memories

This paper presents program pulse characterization in an 8-Mb BJT-selected phase-change memory test chip. Experimental results of the impact of the bit-line resistance over programming pulse efficiency are provided. Furthermore, in order to compensate for spreads in cell physical parameters in an array portion, a non-conventional staircase-down program pulse is proposed and experimentally evaluated.

4-Mb MOSFET-selected /spl mu/trench phase-change memory experimental chip

A /spl mu/trench Phase-Change Memory (PCM) cell with MOSFET selector and its integration in a 4-Mb experimental chip fabricated in 0.18-/spl mu/m CMOS technology are presented. A cascode bitline biasing scheme allows read and write voltages to be fed to the addressed storage elements with the required accuracy. The high-performance capabilities of PCM cells were experimentally investigated. A read access time of 45 ns was measured together with a write throughput of 5 MB/s, which represents an improved performance as compared to NOR Flash memories. Programmed cell current distributions on the 4-Mb array demonstrate an adequate working window and, together with first endurance measurements, assess the feasibility of PCMs in standard CMOS technology with few additional process modules.

Vlsi programmable digital filter for video signal processing

High speed digital filtering is required in real time video signal processing, as well as high order filters are needed to match television studio signal quality. The hardware complexity involved by such system constraints may be faced by a two-fold approach, concerning both the architecture and the technological aspects of a specific electronics device devoted to the above task.This article deals with a processor especially developed for the purpose of fast digital video signal applications, such as filtering, equalization, interpolation and so on. The nonrecursive transposed F.I.R. (Finite Impulse Response) structure has been selected, which exhibits a linear phase behavior. A novel approach has been developed for the multipliers implementation, by optimizing an EPROM based look-up table storing the products between all video samples and the filter coefficients significant bits, resulting in a programmable system.TheProgrammable Filter Processor has been designed with a high level of parallelism and pipelining and a 1.2 µm CMOS EPROM, single metal technology has been employed for the integration process of the chip. This has been successfully production-tested for 40 Msamples/s throughput rate, thus both allowing to meet most video filtering applications and demonstrating the potentialities of nonvolatile memory technologies in embedded applications.Moreover multiple devices can be interconnected to yield multiprocessor structures for more demanding performances such as, cascaded or longer filters, input signal precision extension, computation improved accuracy, increased throughput rate, and two-dimensional signal processing.

Flash Memory Testing

This chapter is not aimed at providing a complete testing theory about Flash; its objective is to present and analyze the most critical aspects related to Flash testing, the tools and methods to improve their testability; to give an idea of the test flow, and of its relation with the excellent quality and reliability that Flash have reached. Aspects related to test cost and productivity are also presented.