Giuseppe Alia

A VLSI modulo m multiplier

A novel method to compute the exact digits of the modulo m product of integers is proposed, and a modulo m multiply structure is defined. Such a structure can be implemented by means of a few fast VLSI binary multipliers, and a response time of about 150-200 ns to perform modular multiplications with moduli up to 32767 can be reached. A comparison to ROM-based structures is also provided. The modular multiplier has been evaluated asymptotically, according to the VLSI complexity theory, and it turned out to be an optimal design. This structure can be used to implement a residue multiplier in arithmetic structures using residue number systems (RNSs). The complexity of this residue multiplier has been evaluated and lower complexity figures than for ROM-based multiply structures have been obtained under several hypotheses on RNS parameters. >

On the lower bound to the VLSI complexity of number conversion from weighted to residue representation

A lower bound AT/sup 2/= Omega (n/sup 2/) for the conversion from positional to residue representation is derived according to VLSI complexity theory, and existing solutions for the same problem are briefly reviewed in the light of such a bound. A VLSI system is proposed, one that operates according to a pipeline scheme and works asymptotically emulating an optimal structure, independently of residue number system parameters. This solution has been applied to a design of specific size (64-b input stream), and it has been found that a single CMOS custom chip can implement the design with a throughput of one residue representation every 30-40 ns. >

Sign detection in residue arithmetic units

Abstract The parallelism of computation, that characterizes some operations in residue number systems (RNS), is heavily reduced in operations as division, magnitude and sign detection, since numbers must be converted to the weighted system thus reducing efficiency, in spite of the efforts to speed up the conversion. In this work the problem of detecting the sign of numbers represented in RNS is considered and a procedure is devised, which keeps numbers in residue notation, and requires a redundant modulus mp+1⩾2. A sign detecting circuit is also designed that, merely to speed up the operation, exploits a further redundant modulus mr⩾p in the signed number representation. Circuit response time is evaluated, both from the complexity point of view and in a finite case, where 50 gate delays are estimated for a range [−2 64 , 2 64 −1] .

NEUROM: a ROM based RNS digital neuron

In this work, a fast digital device is defined, which is customized to implement an artificial neuron. Its high computational speed is obtained by mapping data from floating point to integer residue representation, and by computing neuron functions through residue arithmetic operations, with the use of table look-up techniques. Specifically, the logic design of a residue neuron is described and complexity figures of area occupancy and time consumption of the proposed device are derived. The approach was applied to the logic design of a residue neuron with 12 inputs and with a Residue Number System defined in such a way as to attain an accuracy better than or equal to the accuracy of a 20-bit floating point system. The proposed design (NEUROM) exploits the RNS carry independence property to speed up computations, in addition it is very suitable for using look-up tables. The response time of our device is about 8 x T(ACC), where T(ACC) is the ROM access time. With a value of T(ACC) close to the 10 ns allowed by the current ROM technology, the proposed neuron responds within 80 ns, NEUROM is therefore the neuron device proposed in the literature which allows for maximum throughput. Moreover, when a pipeline mode of operation is adopted, the pipeline delay can assume a value as low as about 14 ns. In the case study considered, the total amount of ROM is about 5.55 Mbits. Thus, using current technology, it is possible to integrate several residue neurons into a single VLSI chip, thereby enhancing chip throughput. The paper also discusses how this amount of memory could be reduced, at the expense of the response time.

A VLSI structure forX(modm) operation

AbstractHigh-computing speed and modularity have made RNS-based arithmetic processors attractive for a long time, especially in signal processing, where additions and multiplications are very frequent. The VLSI technology renewed this interest because RNS-based circuits are becoming more feasible; however, intermodular operations degradate their performance and a great effort results on this topic. In this paper, we deal with the problem of performing the basic operationX(modm), that is the remainder of the integer divisionX/m, for large values of the integerX, following an approximating and correcting approach, which guarantees the correctness of the result.We also define a structure to computeX(modm) by means of few fast VLSI binary multipliers, which is exemplified for 32-bit long numbers, obtaining a total response time lower than 200 nsec. Furthermore, such a structure is evaluated in terms of VLSI complexity and area and time figuresA=ϑ(n2Tm2) andT=ϑ(TM) for the parameterTM in

A fast near optimum VLSI implementation of FFT using residue number systems

[\log n,\sqrt n ]

Fast modular exponentiation of large numbers with large exponents

are derived. A simple positional-to-residue converter is finally presented, based on this structure; it improves some complexity results previously obtained by authors.

Logic Design of a Fast Circuit for Iterative Additions in Redundant Hybrid Number Systems

Abstract Special purpose hardware devices devoted to display families of curves are very attractive when high performance graphic tools are to be designed. In this paper an architecture well suited for fast hardware curve generators is proposed, mainly based on the use of vector generators and ROMs. Curve graphs are approximated by polygonal lines, the extremes of which and a selected subset of vertices can be obtained with the required precision. Output rate is shown to be very close to available vector generators rate. As an example, a device adopting this architecture has been designed for the generation of conic and exponential curves. Precision figures have been obtained in the hypothesis that the generator hardware complexity allows a single chip implementation. The architecture is easily extensible to three-dimensional curves.