Glenn R Young

Inclusive cross section and double helicity asymmetry for pi^0 production in

The PHENIX experiment presents results from the RHIC 2006 run with polarized p + p collisions at root s = 62.4 GeV, for inclusive pi(0) production at midrapidity. Unpolarized cross section results are measured for transverse momenta p(T) = 0.5 to 7 GeV/c. Next-to-leading order perturbative quantum chromodynamics calculations are compared with the data, and while the calculations are consistent with the measurements, next-to-leading logarithmic corrections improve the agreement. Double helicity asymmetries A(LL) are presented for p(T) = 1 to 4 GeV/c and probe the higher range of Bjorken x of the gluon (x(g)) with better statistical precision than our previous measurements at root s = 200 GeV. These measurements are sensitive to the gluon polarization in the proton for 0.06 < x(g) < 0.4.

p^+ p

The time interval measurement system of the WA-98 calorimeter is presented. This system consists of a constant fraction discriminator (CFD), a variable delay circuit, a time-to-amplitude converter (TAC), and a Wilkinson analog-to-digital converter (ADC) all realized in a 1.2-/spl mu/m N-well CMOS process. These circuits measured the time interval between a reference logic signal and a photomultiplier tube (PMT) signal that had amplitude variations of 100:1 and 10-ns rise and fall times. The system operated over the interval range from 2 ns to 200 ns with a resolution of /spl sim//spl plusmn/300 ps including all walk and jitter components. The variable delay circuit allowed the CFD output to be delayed by up to 1 /spl mu/s with a jitter component of /spl sim/0.04% of the delay setting. These circuits operated with a 5-V power supply. Although this application was in nuclear physics instrumentation, these circuits could also be useful in other scientific measurements, medical imaging, automatic test equipment, ranging systems, and industrial electronics.

collisions at

A custom CMOS analog to digital converter was designed and a prototype 8-channel ADC ASIC was fabricated in a 1.2 /spl mu/m process. The circuit uses a Wilkinson-type architecture which is suitable for use in multi-channel applications such as the PHENIX detector. The ADC design features include a differential positive-ECL input for the high speed clock and selectable control for 11 or 12-bit conversions making it suitable for use in multiple PHENIX subsystems. Circuit topologies and ASIC layout specifics, including power consumption, maximum clock speed, INL, and DNL are discussed. The ADC performed to 11-bit accuracy.

\sqrt{s}=62.4

Two monolithic circuits developed for readout of a 10000 element lead glass calorimeter are described. The first contains 8 channels with each channel comprising a charge integrating amplifier, two output amplifiers with gains of one and eight, a timing filter amplifier and a constant fraction discriminator. This IC also contains a maskable, triggerable calibration pulser and circuits needed to form 2 by 2 and 4 by 4 energy sums used to provide trigger signals. The second IC is a companion to the first and contains 16 analog memory channels with 16 cells each, eight time-to-amplitude converters and a 24-channel analog-to-digital converter. The use of the analog memories following the integration function eliminates the need for delay cables preceding it. Characterizations of prototypes are reported, and features included to ease integration of the ICs into a readout system are described.<<ETX>>

GeV

A monolithic, CMOS, constant-fraction discriminator (CFD) was designed and fabricated in a 1.2-/spl mu/, N-well process. This circuit used an on-chip, distributed R-C delay line to realize the constant-fraction shaping. The delay line was constructed of a 4.8-/spl mu/ wide, 500-/spl mu/ long serpentine layer of polysilicon above a grounded second layer of polysilicon. This line generated about 1.1 ns of delay for a 5-ns risetime signal with a slope degradation of only 15%. The CFD also featured dc feedback for both the arming and zero-crossing discriminators to eliminate timing errors caused by offsets. The entire circuit, including the delay line, required an area of 200 /spl mu//spl times/950 /spl mu/. The timing walk for 5-ns risetime signals over the dynamic range from -20 mV to -2 V was less than /spl plusmn/150 ps. Each channel of the CFD consumed /spl sim/15 mW from a single 5-V supply.

An integrated CMOS time interval measurement system with subnanosecond resolution for the WA-98 calorimeter

Abstract The RICH detector of the PHENIX experiment at RHIC is currently under construction. Its main function is to identity electron tracks in a very high particle density, about 1000 charged particles per unit rapidity, expected in the most violent collisions at RHIC. The design and construction status of the detector and its expected performance are described.

A multi-channel ADC for use in the PHENIX detector

A programmable analog memory address list manager has been developed for use with all analog memory-based detector subsystems of PHENIX. The unit provides simultaneous read/write control, cell write-over protection for both a Level-1 trigger decision delay and digitization latency, and re-ordering of AMU addresses following conversion, at a beam crossing rate of 105 ns. Addresses are handled such that up to 5 Level-1 (LVL-1) events can be maintained in the AMU without write-over. Data tagging is implemented for handling overlapping and shared beam-event data packets. Full usage in all PHENIX analog memory-based detector subsystems is accomplished by the use of detector-specific programmable parameters-the number of data samples per valid LVL-1 trigger and the sample spacing. Architectural candidates for the system are discussed with emphasis on implementation implications. Details of the design are presented including application specifics, timing information, and test results from a full implementation using field programmable gate arrays (FPGAs).

Monolithic circuits for the WA98 lead class calorimeter

Measurements of the azimuthal anisotropy of high-p(T) neutral pion (pi(0)) production in Au+Au collisions at s(NN)=200 GeV by the PHENIX experiment are presented. The data included in this article were collected during the 2004 Relativistic Heavy Ion Collider running period and represent approximately an order of magnitude increase in the number of analyzed events relative to previously published results. Azimuthal angle distributions of pi(0) mesons detected in the PHENIX electromagnetic calorimeters are measured relative to the reaction plane determined event-by-event using the forward and backward beam-beam counters. Amplitudes of the second Fourier component (v(2)) of the angular distributions are presented as a function of pi(0) transverse momentum (p(T)) for different bins in collision centrality. Measured reaction plane dependent pi(0) yields are used to determine the azimuthal dependence of the pi(0) suppression as a function of p(T), R-AA(Delta phi,p(T)). A jet-quenching motivated geometric analysis is presented that attempts to simultaneously describe the centrality dependence and reaction plane angle dependence of the pi(0) suppression in terms of the path lengths of hypothetical parent partons in the medium. This set of results allows for a detailed examination of the influence of geometry in the collision region and of the interplay between collective flow and jet-quenching effects along the azimuthal axis.

A monolithic, constant-fraction discriminator using distributed R-C delay line shaping

The TGV32, a 32-channel preamplifier–multiplicity discriminator chip for the multiplicity vertex detector (MVD) at PHENIX, is a unique silicon preamplifier in that it provides both an analog output for storage in an analog memory and a weighted summed-current output for conversion to a channel multiplicity count. The architecture and test results of the chip are presented. Details about the design of the preamplifier, discriminator, and programmable digital–analog converters performance as well as the process variations are presented. The chip is fabricated in a 1.2 μm, n-well, complementary metal–oxide–semiconductor process.

Ring imaging Cherenkov detector of PHENIX experiment at RHIC

This paper describes TGLD, a charge readout chip for the PHENIX Pad Chamber (PC) subsystem at Brookhaven National Laboratorys Relativistic Heavy Ion Collider (RHIC) in Upton, NY. Due to the PCs high channel density, the TGLD and associated circuitry operate within the active detector region as permanent, zero access components, with remote set-up and test during collider operation. The TGLD design accommodates varying pad capacitance and charge gain for three detector subassemblies that detect particles at three different distances from the PHENIX collision vertex. The design also provides adjustable discrimination thresholds from MIP/10 to 2 MIP (Minimum Ionizing Particle). Three TGLD chips operate with a complimentary digital memory unit (DMU) to form 48 channel low power, low mass, readout cards. Partitioning of readout electronics and address control for robust remote operation are discussed. Component and system test results are also reported.