Gooitzen Siemen van der Wal

A VLSI pyramid chip for multiresolution image analysis

Advanced techniques in image processing and computer vision increasingly require that image data be represented at multiple resolutions and at multiple sample rates. Application areas for such pyramid image representations include image compression, image enhancement, motion analysis, and object recognition.We have developed a VLSI chip, called PYR, to perform the standard filter and resampling operations required in pyramid and inverse pyramid transforms for these applications. The PYR chip processes image samples sequentially, in raster scan format, so is suited for pipeline architectures. The user can choose from a set of standard filters, through software control, to construct Gaussian, Laplacian, Subband, and related pyramid structures.A unique feature of the design is that it includes timing signals that are passed with the image data. These signals coordinate successive processing steps in a pipeline system as image sizes and sample rates change. The chip also includes circuits for edge extension and image addition, and it can be run in “spread tap” mode to provide twice the standard sample density.The PYR chip is implemented in standard cell technology. At a clock rate of 15 MHz, a single chip can simultaneously construct a Gaussian and a Laplacian pyramid from a 512 by 480 image in 22.7 msec (44 frame/second).

Real Time Pyramid Transform Architecture

This paper describes an architecture for creating pyramid transforms of real time video images. A powerful preprocessor can be designed with this architecture by representing the image data in a form most suitable for the application. The Burt pyramid algorithm [1], an efficient method for transforming video images into hierarchical representation, is an example of an effective transform. A programmable version of such a preprocessor, occupying two Multibus* boards, was built at low cost using available hardware. This unit can perform the basic pyramid trans-form on 256 x 240 images in real time. More complex and/or multiple transforms can be performed at reduced data rate by passing data through the unit several times, or can be performed in real time by passing data through multiple units. Because the preprocessor is programmable, the system is easily configured to perform several different pyramid transforms, or the appropriate inverse transforms. Algorithms can be developed to reduce edge effects by modifying the edges of the image before applying the transform. The preprocessor can be programmed to insert time delays into the system, which is useful in the display of the results. Image processing system, design can be simplified by using the preprocessor to significantly reduce the computational requirements of the main processor. The proposed architecture, suitable for system integration, could lead to the availability of low cost, efficient image processing systems.

Technical overview of the Sarnoff Acadia II vision processor

The Sarnoff Acadia® II is a powerful vision processing SoC (System-on-a-Chip) that was specifically developed to support advanced vision applications where system size, weight and/or power are severely constrained. This paper, targeted at vision system developers, presents a detailed technical overview of the Acadia® II, highlighting its architecture, processing capabilities, memory and peripheral interfaces. All major subsystems will be covered, including: video preprocessing, specialized vision processing cores for multi-spectral image fusion, multi-resolution contrast normalization, noise coring, image warping, and motion estimation. Application processing via the MPCore®, an integrated set of four ARM®11 floating point processors with associated peripheral interfaces is presented in detail. The paper will emphasize the programmability of the Acadia® II, while describing its ability to provide state-of-the-art realtime image processing in a small, power optimized package.*The Sarnoff Acadia II is a powerful vision processing SoC (System-on-a-Chip) that was specifically developed to support advanced vision applications where system size, weight and/or power are severely constrained. This paper, targeted at vision system developers, presents a detailed technical overview of the Acadia II, highlighting its architecture, processing capabilities, memory and peripheral interfaces. All major subsystems will be covered, including: video preprocessing, specialized vision processing cores for multi-spectral image fusion, multi-resolution contrast normalization, noise coring, image warping, and motion estimation. Application processing via the MPCore, an integrated set of four ARM11 floating point processors with associated peripheral interfaces is presented in detail. The paper will emphasize the programmability of the Acadia II, while describing its ability to provide state-of-the-art realtime image processing in a small, power optimized package.

Implementing real-time imaging systems using the Sarnoff Acadia II vision processor

Vision system designers often face the daunting challenge of implementing powerful image processing capabilities in severely size, weight and power constrained systems. Multi-sensor fusion, image stabilization, image enhancement, target detection and object tracking are fundamental processing techniques required by UAVs (Unmanned Aerial Vehicles), smart cameras, weapon sights, and vehicle situational awareness systems. All of these systems also process non-vision data while communicating large amounts of information elsewhere. To meet their demanding requirements, Sarnoff developed the Acadia® II System-on-a-Chip, combining dedicated image processing cores, four ARM®11 processors and an abundance of peripherals in a single Integrated Circuit. This paper will describe how to best use the power of the Acadia® II as both an all-in-one image processor and as a general purpose computer for performing other critical non-vision tasks, such as flight control and system-to-system communication.