Gopalakrishnan Ramalingam

Magnitude and Origin of Electrical Noise at Individual Grain Boundaries in Graphene

Grain boundaries (GBs) are undesired in large area layered 2D materials as they degrade the device quality and their electronic performance. Here we show that the grain boundaries in graphene which induce additional scattering of carriers in the conduction channel also act as an additional and strong source of electrical noise especially at the room temperature. From graphene field effect transistors consisting of single GB, we find that the electrical noise across the graphene GBs can be nearly 10 000 times larger than the noise from equivalent dimensions in single crystalline graphene. At high carrier densities (n), the noise magnitude across the GBs decreases as ∝1/n, suggesting Hooge-type mobility fluctuations, whereas at low n close to the Dirac point, the noise magnitude could be quantitatively described by the fluctuations in the number of propagating modes across the GB.

Alternative Route to Silicene Synthesis via Surface Reconstruction on h-MoSi2 Crystallites

Silicene is a two-dimensional material with a Dirac-type band structure and it is particularly attractive due to its potential for integration with Si-based technology. The primary focus has been to grow single silicene layers and understand how the electronic structure is affected by the substrate and the phase transition between low- and high-buckling configurations. Typically, silicene is synthesized by depositing monolayer amounts of silicon onto a heated Ag(111) surface; however, other growth substrates such as Ir(111) and ZrB2 have been studied recently. We present a novel route for silicene synthesis via a high-temperature surface reconstruction of hexagonal-MoSi2 nanocrystallites. The h-MoSi2 crystallites are formed by annealing of thin Mo-layers on Si(100)-(2 × 1) and their crystallographic orientation is controlled via an epitaxial relation with the Si-substrate. The (0001) plane of h-MoSi2 is comprised of Si-hexagons with a Mo atom residing in the center. Annealing above approximately 650 °C causes the (0001) plane to undergo a surface reconstruction process leaving a honeycomb pattern on the surface of these crystallites as shown by scanning tunneling microscopy. We define this surface layer as a silicene-like reconstruction (SLR), and a detailed geometric analysis of our structure yields a perfect match with the (√3 × √3)R30° silicene superstructure in a low-buckled configuration (ABA̅). Scanning tunneling spectroscopy data of the SLR, Si(001)-(2 × 1) and h-MoSi2 surfaces agree with this interpretation. The formation of this structure on a transition metal silicide opens up the opportunity for integration into Si-based devices without the necessity for a transfer scheme.

Origin of 1/f noise in graphene produced for large-scale applications in electronics

The authors report a detailed investigation of the flicker noise (1/f noise) in graphene films obtained from chemical vapour deposition (CVD) and chemical reduction of graphene oxide. The authors find that in the case of polycrystalline graphene films grown by CVD, the grain boundaries and other structural defects are the dominant source of noise by acting as charged trap centres resulting in huge increase in noise as compared with that of exfoliated graphene. A study of the kinetics of defects in hydrazine-reduced graphene oxide (RGO) films as a function of the extent of reduction showed that for longer hydrazine treatment time strong localised crystal defects are introduced in RGO, whereas the RGO with shorter hydrazine treatment showed the presence of large number of mobile defects leading to higher noise amplitude.

Electrochemical Integration of Graphene with Light-Absorbing Copper-Based Thin Films

We present an electrochemical route for the integration of graphene with light-sensitive copper-based alloys used in optoelectronic applications. Graphene grown using chemical vapor deposition (CVD) transferred to glass is found to be a robust substrate on which photoconductive CuxS films of 1–2 μm thickness can be deposited. The effect of growth parameters on the morphology and photoconductivity of CuxS films is presented. Current–voltage (I–V) characterization and photoconductivity decay experiments are performed with graphene as one contact and silver epoxy as the other.