Gordian Prescher

The digital silicon photomultiplier — Principle of operation and intrinsic detector performance

We developed a fully digital implementation of the Silicon Photomultiplier. The sensor is based on a single photon avalanche photodiode (SPAD) integrated in a standard CMOS process. Photons are detected directly by sensing the voltage at the SPAD anode using a dedicated cell electronics block next to each diode. This block also contains active quenching and recharge circuits as well as a one bit memory for the selective inhibit of detector cells. A balanced trigger network is used to propagate the trigger signal from all cells to the integrated time-to-digital converter (TDC). Photons are detected and counted as digital signals, thus making the sensor less susceptible to temperature variations and electronic noise. The integration with CMOS logic has the added benefit of low power consumption and possible integration of data post-processing. In this paper, we discuss the sensor architecture and present first measurements of the technology demonstrator test chip.

The digital Silicon Photomultiplier — A novel sensor for the detection of scintillation light

We developed a fully digital Silicon Photomultiplier (dSiPM) of 3.8 mm × 3.3 mm in size containing 8188 individual Geiger-mode cells. Each detected photon is directly converted into a digital signal in each of the Geiger-mode cells of the sensor. In addition, the complete trigger logic and a time-to-digital converter are integrated into the sensor. To show the performance of the sensor, LYSO crystals of different sizes were coupled to the sensor. The coincidence timing resolution for 3 mm × 3 mm × 5 mm LYSO crystals using a 22Na source amounts to 153 ps FWHM. The energy resolution at 511 keV was determined to be 10.7 % for 4 mm × 4 mm × 22 mm crystals. It is shown that saturation correction can be done without prior need for sensor calibration. The temperature dependence of the photon detection efficiency was found to be -0.6 %/°C including the temperature variation of the light output of LYSO.

The digital silicon photomultiplier — System architecture and performance evaluation

In this paper we present the first fully digital implementation of the Silicon Photomultiplier. The chip design is based on the technology demonstrator chip presented in [3]. The new sensor represents a self-contained detector including a JTAG controller for configuration and test, single-ended and differential clock and test input signals, an integrated acquisition controller and two serial data outputs. The sensor is based on a single photon avalanche photodiode (SPAD) technology integrated in a standard CMOS process flow. Photons are detected directly by sensing the voltage at the SPAD terminal using a dedicated cell electronics block next to each diode. This block also contains active quenching and recharge circuits as well as a one bit memory for the selective activation of individual detector cells. A balanced trigger network is used to propagate the trigger signal from all cells to the two integrated time-to-digital converters. Photons are detected and counted as digital signals, thus making the sensor less susceptible to temperature variations and electronic noise. The resulting data packets are transferred to the readout system through a serial data interface. In this paper, we discuss the new sensor architecture and evaluate its performance.