Gordon B. Steven

HARP: a parallel pipelined RISC processor

Abstract HARP (the Hatfield RISC processor) is a reduced instruction set processor being developed at Hatfield Polytechnic, UK. The major aim of the HARP project is to develop a RISC processor capable of a sustained instruction execution rate in excess of one instruction per cycle. Investigations to date support the hypothesis that this goal can be achieved by the development of an integrated processor-compiler pair in which the processor is specifically designed to support low-level parallelism identified by the compiler. This paper describes the HARP architectural model and discusses those features which support parallel instruction execution. Parallelism is provided in the hardware by multiple instruction pipelines which execute independent RISC-like instructions simultaneously. The principal techniques employed to exploit the available parallelism are efficient pipelining, register bypassing, optional register writeback and conditional execution of instructions. Examples are given which illustrate the effectiveness of these techniques in increasing the performance of HARP.

A superscalar architecture to exploit instruction level parallelism

Abstract If a high-performance superscalar processor is to realise its full potential, the compiler must re-order or schedule the object code at compile time. This scheduling creates groups of adjacent instructions that are independent and which therefore can be issued and executed in parallel at run time. This paper provides an overview of the Hatfield Superscalar Architecture (HSA), a multipleinstruction-issue architecture developed at the University of Hertfordshire to support the development of high-performance instruction schedulers. The long-term objective of the HSA project is to develop the scheduling technology to realise an order of magnitude performance improvement over traditional RISC designs. The paper also presents results from the first HSA instruction scheduler that currently achieves a speedup of over three compared to a classic RISC processor.

Dynamic branch prediction using neural networks

Dynamic branch prediction in high-performance processors is a specific instance of a general time series prediction problem that occurs in many areas of science. In contrast, most branch prediction research focuses on two-level adaptive branch prediction techniques, a very specific solution to the branch prediction problem. An alternative approach is to look to other application areas and fields for novel solutions to the problem. In this paper, we examine the application of neural networks to dynamic branch prediction. Two neural networks are considered: a lecturing vector quantisation (LVQ) Network and a backpropagation network. We demonstrate that a neural predictor can achieve misprediction rates comparable to conventional two-level adaptive predictors and suggest that neural predictors merit further investigation.

HARP: a VLIW RISC processor

HARP, (the Hatfield RISC processor), is a reduced instruction set processor. The major aim of the HARP project is to develop a VLIW (very long instruction word) RISC (reduced instruction set computer) processor capable of a sustained instruction execution rate in excess of one instruction per cycle by the parallel execution of RISC-type instructions. Investigations to date support the hypothesis that this goal can be achieved by the development of an integrated processor-compiler pair designed to support low-level parallelism identified by the compiler. A description is presented of the HARP architecture and those hardware features which will support parallel instruction execution. Parallelism is provided in the hardware by multiple instruction pipelines which execute independent RISC-like instructions simultaneously. The principal techniques used to exploit the available parallelism are efficient pipelining, register bypassing, optional register writeback, and conditional execution of instructions.<<ETX>>

Utilising low level parallelism in general purpose code: the HARP project

Abstract This paper describes how the distinctive features of the Hatfield RISC Processor (HARP) and its associated compilation techniques are combined to utilise the parallelism available in general purpose code. The overall aim of the HARP project is to produce a processor that can provide a sustained execution rate for non-scientific code in excess of one instruction per cycle. This goal will be accomplished by using a multiple pipelined processor and an optimising compiler. The compiler schedules short RISC-type instructions for the set of parallel pipelines and packs them into long instruction words. The processor fetches long instruction words from an instruction cache and passes the component short instructions through the multiple pipeline structure. The performance of the processor is increased by the use of conditional instruction execution. Conditional execution allows the compiler to schedule more instructions in parallel by overlapping instructions from consecutive basic blocks and by merging two or more blocks.

A novel effective address calculation mechanism for RISC microprocessors

In procedure oriented languages such as Pascal and C, the above addressing modes might be used to access data operands in the run-time environment shown in Fig 1. A single stack pointer, pointing to the top of the run-time stack, is used to access all local variables in the current stack frame. A second general purpose register, SB, is used in a similar fashion to access global variables declared at the outermost textual level of a program. The majority of operand accesses therefore involve adding either a constant or the contents of a general purpose register to either SP or SB.

Hades-towards the design of an asynchronous superscalar processor

This paper uses Hades, a generic processor architecture aimed at single and multiple-instruction-issue asynchronous implementations, to illustrate some of the difficulties encountered in asynchronous processor design. Particular emphasis is placed on a decoupled operand forwarding mechanism which allows the last result of each functional unit to be forwarded to following instructions, yet completely separates forwarding from the register writeback operation.

ALU design and processor branch architecture

Abstract This paper examines the role of the ALU within the context of high-performance processor design. In particular, the functional requirements of various processor branch architectures are evaluated and related to ALU design. The paper demonstrates that the traditional condition code branch mechanism is unsuitable for high-performance, multiple-instruction-issue processor implementations. First, the use of condition codes hinders code motion and therefore inhibits instruction scheduling. Second, the use of condition codes prevents the early resolution of branch conditions and therefore either increases the processor cycle time or the number of branch delay slots. Various alternative branch mechanisms are examined which remove the first restriction. Two of the branch architectures considered are also shown to remove the second problem. In both architectures the crucial factor is that only a single branch condition needs to be evaluated for each branch. Outline designs of a Relational Unit and an ALU which meet the requirements of the two high-performance branch architectures are also presented and compared with traditional ALU and comparator designs.

Addressing mechanisms for VLIW and superscalar processors

Abstract RISC processors employ simple addressing modes which allow memory addresses to be calculated in a single processor cycle. This paper demonstrates that VLIW and Superscalar processor performance can be improved by further simplifying the addressing modes. In particular, the distinctive ORed indexing addressing mechanism employed by the HARP VLIW processor boosts performance by 10%. Register indirect addressing on its own yields a similar performance improvement.

A parallel pipelined processor with conditional instruction execution

In a recent paper by Smith, Lam and Horowitz [1] the concept of boosting was introduced, where instructions from one of the possible instruction streams following a conditional branch were scheduled by the compiler for execution in the basic block containing the branch itself. This paper describes how code from both instruction streams following a conditional branch can be considered for execution in the basic block containing the branch. Branch conditions are stored in Boolean registers and all instructions are conditionally executed based on the value in a Boolean register. The two instruction streams can therefore be executed on complementary values of the same Boolean register.