Gordon P. Pollack

Characteristics and three-dimensional integration of MOSFET's in small-grain LPCVD polycrystalline Silicon

Building on nearly two decades of reported results for MOSFETs fabricated in small-grain polycrystalline silicon, a design methodology is developed that yields devices which have low threshold voltage, high drive current, low leakage current, tight parameteric control, and reduced topology, while requiring no nonstandard materials, processes, and tools. Design criteria and device performance are discussed, grain boundary characterization techniques are described, technological issues pertinent to VLSI implementation are investigated, and long-term device reliability is studied. The potential applications of the polysilicon MOSFETs in high-density dRAM and sRAM are explored. The successful implementation of an experimental stacked CMOS 64K static RAM proves the utility of these devices for three-dimensional integration in a VLSI environment.

Single-transistor latch in SOI MOSFETs

A single-transistor latch phenomenon observed in silicon-on-insulator (SOI) MOSFETs is reported. This latch effect, which occurs at high drain biases, is an extreme case of floating-body effects which are present in SOI MOSFETs. The floating body results in positive feedback between the impact ionization current, body-to-source diode forward bias, and transistor currents. At large drain voltages, this positive feedback can maintain a high-drain-to-source current even when the MOS gate is biased well below its threshold voltage.<<ETX>>

A trench transistor cross-point DRAM cell

A 1T DRAM cell with both the transistor and the capacitor fabricated on the sidewalls of a deep trench is described. Trench Transistor Cell (TTC) fabrication and characterization are discussed.

Modeling of the subthreshold characteristics of SOI MOSFETs with floating body

n-channel SOI MOSFETs with floating bodies show a threshold voltage shift and an improvement in subthreshold slope at high drain biases. The magnitude of this effect depends on the device parameters and the starting SOI substrate. A simple device model is presented that explains the observed characteristics to be due to MOS back-bias effects resulting from the positively charged floating body. The improvement in the subthreshold slope is the outcome of positive feedback between the body potential and the transistor channel current. >

Total Dose Hardening of Buried Insulator in Implanted Silicon-on-Insulator Structures

Total dose characteristics of the buried insulator in implanted silicon-on-insulator (SOI) substrates have been studied using MOS transistors. The threshold voltage shift of the parasitic back channel transistor, which is controlled by charge trapping in the buried insulator, is reduced by lowering the oxygen dose as well as by an additional nitrogen implant, without degrading the front channel transistor characteristics. The improvements in the radiation characteristics of the buried insulator are attributed to the decrease in the buried oxide thickness or to the presence of the interfacial oxynitride layer formed by the oxygen and nitrogen implants.

Total Dose Characterizations of CMOS Devices in Oxygen Implanted Silicon-on-Insulator

The total dose characteristics of CMOS devices fabricated in oxygen implanted buried oxide silicon-on-insulator (SOI) substrates with different post-implant annealing processes are studied. The threshold voltage shift, subthreshold slope degradation and mobility degradation of front channel SOI/CMOS devices are measured to be the same as those of bulk devices processed identically. Negative substrate bias lowers the threshold voltage shift of back channel SOI transistors, while not affecting the front channel characteristics. Under present processing conditions, the radiation characteristics of front channel devices are independent of the postoxygen-implant annealing temperature. Oxygen precipitates at the silicon/buried oxide interface enhance interface state generation of the back channel devices during irradiation.

Characteristics and Three-Dimensional Integration of MOSFET's in Small-Grain LPCVD Polycrystalline Silicon

Building on nearly two decades of reported results for MOSFETs fabricated in small-grain polycrystalline silicon, a design methodology is developed that yields devices which have low threshold voltage, high drive current, low leakage current, tight parameteric control, and reduced topology, while requiring no nonstandard materials, processes, and tools. Design criteria and device performance are discussed, grain boundary characterization techniques are described, technological issues pertinent to VLSI implementation are investigated, and long-term device reliability is studied. The potential applications of the polysilicon MOSFETs in high-density dRAM and sRAM are explored. The successful implementation of an experimental stacked CMOS 64K static RAM proves the utility of these devices for three-dimensional integration in a VLSI environment.

The characteristics of CMOS devices in oxygen-implanted silicon-on-insulator structures

The characteristics of CMOS devices fabricated in oxygen-implanted silicon-on-insulator (SOI) substrates with different oxygen doses are studied. The results show that transistor junction leakage currents are improved by orders of magnitude when the oxygen dose is decreased from 2.25*10/sup 18/ cm/sup -2/ to 1.4*10/sup 18/ cm/sup -2/ . The floating-body effect, i.e. transistor turn-on at lower gate voltage with dramatic improvement in subthreshold slope when the drain voltage is increased, is enhanced by the reduction in leakage current and hence the oxygen dose. In SOI substrates implanted with 1.4*10/sup 17/ cm/sup -2/ oxygen dose and annealed at 1150 degrees C, back-channel mobilities are decreased by several orders of magnitude compared to the mobilities in the precipitate-free silicon film. These device characteristics are correlated with the microstructure at the silicon-buried-oxide interface, which is controlled by oxygen implantation and post-oxygen-implantation anneal. >

Recent advances in process synthesis for semiconductor devices

Recently, work has been started on a new methodology, called process synthesis, that has the potential to revolutionize integrated circuit (IC) process design in the same way that ASIC and microelectronics manufacturing science and technology (MMST) revolutionized circuit design and factory operation. This paper provides an overview of process synthesis, discusses synthesis methodologies, potential roadblocks to execution of this strategy, and presents recent progress in developing this capability.

Ultra-thin film SOI/CMOS with selective-epi source/drain for low series resistance, high drive current

A self-aligned selective epitaxial technique is used to overcome the high source/drain resistance problem in ultra-thin film SOI/CMOS devices. Very low series resistances, comparable to those for bulk CMOS devices, are demonstrated with this selective-epi source/drain.<<ETX>>