Goutam Kumar Dalapati

Impact of strained-Si thickness and Ge out-diffusion on gate oxide quality for strained-Si surface channel n-MOSFETs

Surface channel strained-silicon MOSFETs on relaxed Si/sub 1-x/Ge/sub x/ virtual substrates (VSs) have been established as an attractive avenue for extending Si CMOS performance as dictated by Moores law. The performance of a surface channel Si n-MOSFET is significantly influenced by strained Si/SiO/sub 2/ interface quality. The effects of Ge content (20, 25, and 30%) in the VS and strained-Si thickness (6, 5.5, 4.7, and 3.7 nm) on the strained Si/SiO/sub 2/ interface have been investigated. The interface trap density was found to be proportional to the Ge content in the VS. Fixed oxide charge density reduces to a lower limit at higher strained-Si thickness for any Ge content in the VS, and the value increases as the strained-Si thickness is reduced. There is a high concentration of interface trap charge and fixed oxide charge present for devices with a strained-Si channel thickness below 4.7 nm. To investigate the effect of strained Si/SiO/sub 2/ interface quality on MOSFET devices fabricated using a high-temperature CMOS process, the performance of surface channel n-MOSFETs has been correlated with channel thickness. It is noted that the drain-current rapidly decreases at low gate voltages for channel thicknesses less than 4.7 nm. The performance of both MOS capacitors and MOSFETs degraded below a strained-Si thickness of 4.7 nm irrespective of the Ge content in the VS even up to 30%. TCAD simulations have been carried out to analyze the effect of strained Si/SiO/sub 2/ interface on electrical characteristics. Performance degradation in thin strained-Si channels is primarily attributed to gate oxide quality. The out-diffused Ge accumulates at the strained Si/SiO/sub 2/ interface, introducing a significant amount of interface traps and fixed oxide charges during thermal oxidation. Interface trap density and fixed oxide charge density significantly increased when the Ge concentration at the surface becomes more than 6%. This paper suggests that a minimum strained-Si layer thickness of /spl sim/ 5.0 nm is required to achieve a good strained Si/SiO/sub 2/ interface quality for surface channel strained-Si n-MOSFETs, fabricated using a high thermal budget CMOS process.

Nanocrystal engineering of sputter grown CuO photocathode for visible light driven electrochemical water splitting

Cupric oxide (CuO) thin film was sputtered onto fluorine-doped tin oxide (FTO) coated glass substrate and incorporated into a photoelectrochemical (PEC) cell as a photocathode. Through in situ nanocrystal engineering, sputtered CuO film shows an improvement in its stability and photocurrent generation capability. For the same CuO film thickness (150 nm), films deposited at a sputtering power of 300 W exhibit a photocurrent of ∼0.92 mAcm(-2) (0 V vs RHE), which is significantly higher than those deposited at 30 W (∼0.58 mAcm(-2)). By increasing the film thickness to 500 nm, the photocurrent is further enhanced to 2.5 mAcm(-2), which represents a photocurrent conversion efficiency of 3.1%. Systematic characterization using Raman, XRD, and HR-TEM reveals that the high sputtering power results in an improvement in CuO film crystallinity, which enhances its charge transport property and, hence, its photocurrent generation capabilities.

Effects of AlAs interfacial layer on material and optical properties of GaAs∕Ge(100) epitaxy

GaAs∕AlAs∕Ge(100) samples grown at 650°C with AlAs interfacial layer thickness of 0, 10, 20, and 30nm were characterized using transmission electron microscopy, secondary ion mass spectrometry (SIMS), and photoluminescence (PL) techniques. SIMS results indicate that the presence of an ultrathin AlAs interfacial layer at the GaAs∕Ge interface has dramatically blocked the cross diffusion of Ge, Ga, and As atoms, attributed to the higher Al–As bonding energy. The optical quality of the GaAs epitaxy with a thin AlAs interfacial layer is found to be improved with complete elimination of PL originated from Ge-based complexes, in corroboration with SIMS results.

Interfacial characteristics and band alignments for ZrO2 gate dielectric on Si passivated p-GaAs substrate

The interfacial characteristics and band alignments of high-k ZrO2 on p-GaAs have been investigated by using x-ray photoelectron spectroscopy and electrical measurements. It has been demonstrated that the presence of Si interfacial passivation layer (IPL) improves GaAs metal-oxide-semiconductor device characteristics such as interface state density, accumulation capacitance, and hysteresis. It is also found that Si IPL can reduce interfacial GaAs-oxide formation and increases effective valence-band offset at ZrO2∕p-GaAs interface. The effective valence-band offsets of ZrO2∕p-GaAs and ZrO2∕Si∕p-GaAs interfaces are determined to be 2.7 and 2.84eV, while the effective conduction-band offsets are found to be 1.67 and 1.53eV, respectively.

Photovoltaic characteristics of p-β-FeSi2(Al)/n-Si(100) heterojunction solar cells and the effects of interfacial engineering

Heterojunction solar cells with Al-alloyed polycrystalline p-type β-phase iron disilicide [p-β-FeSi2(Al)] on n-Si(100) were investigated. The p-β-FeSi2(Al) was grown by sputter deposition and rapid-thermal annealing. Photocurrent of ∼1.8 mA/cm2 and open-circuit voltage of ∼63 mV were obtained for p-β-FeSi2(Al)/n-Si(100)/Ti/Al control cells with indium-tin-oxide (ITO) top electrode. Open-circuit voltage increased considerably once thin Al layer was deposited before amorphous-FeSi2(Al) deposition. Furthermore, device performances were found to improve significantly (∼5.3 mA/cm2 and ∼450 mV) by introducing germanium-nitride electron-blocking layer between ITO and p-β-FeSi2(Al). The improvement is attributed to the formation of epitaxial Al-containing p+-Si at p-β-FeSi2(Al)/n-Si(100) interface and suppressed back-diffusion of photogenerated electrons into ITO.

Characterization of sputtered TiO2 gate dielectric on aluminum oxynitride passivated p-GaAs

Structural and electrical characteristics of sputtered TiO2 gate dielectric on p-GaAs substrates have been investigated. It has been demonstrated that the introduction of thin aluminum oxynitride (AlON) layer between TiO2 and p-GaAs improves the interface quality. X-ray photoelectron spectroscopy and transmission electron microscopy results show that the AlON layer effectively suppresses the interfacial oxide formation during thermal treatment. The effective dielectric constant value is 1.5 times higher for the TiO2∕AlON gate stack compared to directly deposited TiO2 on p-GaAs substrates, with a comparable interface state density. The capacitance-voltage (C-V), current-voltage (I-V) characteristics, and charge trapping behavior of the TiO2∕AlON gate stack under constant voltage stressing exhibit an excellent interface quality and high dielectric reliability, making the films suitable for GaAs based complementary metal-oxide-semiconductor technology.

Reduction of Cu-rich interfacial layer and improvement of bulk CuO property through two-step sputtering for p-CuO/n-Si heterojunction solar cell

Copper-rich interfacial-layer (Cu-rich IL) is formed during sputter deposition of cupric oxide (CuO) layer on silicon (Si). It has significant impact on the performance of p-CuO/n-Si heterojunction solar cells. In this report, CuO films deposited on Si at different RF-power levels using single and two-step RF-sputtering techniques and p-CuO/n-Si heterojunction solar cells have been investigated. Systematic characterization using XPS, AFM, XRD, Raman, and HR-TEM reveal that two-step RF-sputtering technique offers better crystal quality CuO film with thinner Cu-rich IL layer. Photovoltaic (PV) properties with an open-circuit voltage (Voc) of 421 mV, short circuit current (Jsc) of 4.5 mA/cm2, and a photocurrent of 8.3 mA/cm2 have been achieved for the cells prepared using two-step sputtering method, which are significantly higher than that for the solar cells fabricated using a single-step sputtering. The PV properties were further improved by depositing CuO films at higher working pressure with nitrogen dop...

HfOxNy gate dielectric on p-GaAs

Plasma nitridation method is used for nitrogen incorporation in HfO2 based gate dielectrics for future GaAs-based devices. The nitrided HfO2 (HfOxNy) films on p-GaAs improve metal-oxide-semiconductor device characteristics such as interface state density, accumulation capacitance, hysteresis, and leakage current. An equivalent oxide thickness of 3.6 nm and a leakage current density of 10−6 A cm−2 have been achieved at VFB−1 V for nitrided HfO2 films. A nitride interfacial layer (GaAsO:N) was observed at HfO2–GaAs interface, which can reduce the outdiffusion of elemental Ga and As during post-thermal annealing process. Such suppression of outdiffusion led to a substantial enhancement in the overall dielectric properties of the HfO2 film.

Current Status and Future Prospects of Copper Oxide Heterojunction Solar Cells

The current state of thin film heterojunction solar cells based on cuprous oxide (Cu2O), cupric oxide (CuO) and copper (III) oxide (Cu4O3) is reviewed. These p-type semiconducting oxides prepared by Cu oxidation, sputtering or electrochemical deposition are non-toxic, sustainable photovoltaic materials with application potential for solar electricity. However, defects at the copper oxide heterojunction and film quality are still major constraining factors for achieving high power conversion efficiency, η. Amongst the Cu2O heterojunction devices, a maximum η of 6.1% has been obtained by using pulsed laser deposition (PLD) of AlxGa1−xO onto thermal Cu2O doped with Na. The performance of CuO/n-Si heterojunction solar cells formed by magnetron sputtering of CuO is presently limited by both native oxide and Cu rich copper oxide layers at the heterointerface. These interfacial layers can be reduced by using a two-step sputtering process. A high η of 2.88% for CuO heterojunction solar cells has been achieved by incorporation of mixed phase CuO/Cu2O nanopowder. CuO/Cu2O heterojunction solar cells fabricated by electrodeposition and electrochemical doping has a maximum efficiency of 0.64% after surface defect passivation and annealing. Finally, early stage study of Cu4O3/GaN deposited on sapphire substrate has shown a photovoltaic effect and an η of ~10−2%.

Rapid thermal annealing assisted stability and efficiency enhancement in a sputter deposited CuO photocathode

We designed a stable and efficient CuO based photocathode by tuning the crystallinity and surface morphology of films by rapid thermal treatment. The role of the annealing temperature on film crystallinity, optical absorption and grain size is studied. The impact of these parameters upon the photocatalytic water splitting performance of CuO films is investigated. We observed that a higher annealing temperature improves the film crystallinity and increases the grain size of CuO film, which significantly enhance the photocurrent generation capability. Rapid thermal annealing at 550 °C is found the best temperature to achieve the highest PEC performance. The thickness of the CuO photocathodes is also optimized and we observed that 550 nm thick films results in the highest photocurrent of 1.68 mA cm−2. Our optimized CuO photocathode has shown better stability against photo-corrosion and a 30% decrease in the initial value of photocurrent is measured after 15 min, while a 60% decrease in the photocurrent is noticed in case of the as-deposited film.