Graham W. Hills

Sub-0.5-μm polysilicon etching on a MERIE system: a case study in manufacturing

A polysilicon etch process designed for use in manufacturing must yield stable results for critical dimensions, line profile, gate oxide loss, gate oxide damage, defect density, and throughput; all of which must meet the desired specifications for the device being fabricated. A process that meets these requirements has been developed for undoped polysilicon with nominal linewidth of 0.45 micrometers and gate dielectric thickness of 90 angstroms on a single wafer (150 mm) magnetically enhanced reactive ion etch (MERIE) system. The impact of plasma induced charging on device performance is discussed using test results of time dependent dielectric breakdown for structures with polysilicon: gate antenna ratios in the range of 1:1 to 10,000.

Deep trench process performance enhancements in an MERIE reactor

The development of a 16 Mb DRAM capable, deep trench etch in an applied materials P5000E, 200 mm, reactor is discussed in this paper. In order to meet the stringent device requirements extensive system modification, better process control tool development, and process optimization were necessary. The system modification activities have included: (1) a monopolar electrostatic chuck in place of the normal mechanical clamp to reduce trench profile tilt at the wafer edge, (2) an increase in cathode size, and (3) magnetic field modification. Both (2) and (3) improved the trench etch rate uniformity. For better process control, a blue laser diffraction etch rate monitor system has been demonstrated for 0.8 micrometers X 4 to approximately 7 micrometers 16 Mb trenches using two chemistries, HBr/SiF4/He-O2 and HBr/NF3/He-O2. By means of process optimization, both HBr/SiF4/He-O2 and HBr/NF3/He-O2 chemistries are able to meet the requirements for 16 Mb trench.