Greg Sadowski

Low-power networks-on-chip: progress and remaining challenges

After a long period of academic and industrial research, networks-on-chips (NoCs) are starting to be incorporated into commercial multi-processor designs. NoCs have proven themselves to scale better than bus-based designs and they are here to stay. It is still important to note, however, that even well-designed NoCs consume a large portion of a given systems power budget. This brief paper and accompanying presentation discuss what options are available to designers who need to reduce NoC power consumption, their benefits, and their limitations. Techniques discussed here include general NoC system design as well as disruptive interconnect mediums and their associated strategies.

An asynchronous NoC router in a 14nm FinFET library: Comparison to an industrial synchronous counterpart

An asynchronous high-performance low-power 5-port network-on-chip (NoC) router is introduced. The proposed router integrates low-latency input buffers using a circular FIFO design, and a novel end-to-end credit-based virtual channel (VC) flow control for a replicated switch architecture. This asynchronous router is then compared to an AMD synchronous router, in a realistic advanced 14nm FinFET library. This is the first such comparison, to the best of our knowledge, using a real synchronous router baseline already fabricated in several commercial products. Initial post-synthesis pre-layout experiments show dominating results for the asynchronous router, when compared to the synchronous router. In particular, 55% less area and 28% latency improvement are observed for the asynchronous implementation. Also, 88% and 58% savings in idle and active power, respectively, are obtained.

Design and implementation of novel source synchronous interconnection in modern GPU chips

As the architecture of GPU chips evolves to provide higher performance with lower power, new topology of graphics shader engines interconnection to local frame buffers becomes critical. Source synchronous interconnection has been widely adopted in Network-On-Chip (NoC). The SSB bus fabric to transfer data between shader engines and frame buffers adopts more of the globally asynchronous locally synchronous (GALS) design style for a large size GPU chip, in order to deal with the challenge of delivering synchronous high frequencies clocks in the GHz range across full chip. It also reduces the area cost and power consumption on long distance wide width data transfer. In this paper, we present the design structure and physical implementation of a novel source synchronous interconnect network for GALS-style GPU topology. This combines the source synchronous bus lane together with Multiple Data Rate (MDR) structure and much higher transmission clock frequency than shader clock to provide high bandwidth, high speed, low area cost data transmission fabric for GPU chips. We also developed MDR signal bits encoding techniques to reduce the toggle rate of the MDR data nets. With clock gating scheme and MDR signal encoding techniques adapted to the applications, we could further reduce the total power on the SSB transmission fabric.