Gregory Dimitroulakos

An ultra high speed architecture for VLSI implementation of hash functions

Today, security is a topic which attacks the great interest of researchers. Many encryption algorithms have been investigated, and developed in the last years. The research community efforts are also centered to the efficient implementation of them, in both software platforms and hardware devices. This work is related to hash functions FPGA implementation. Two different hash functions are studied: RIPEMD-160 and SHA-1. A high speed architecture is proposed for the implementation of both of them in the same hardware module. The proposed system reaches throughput values equal to 1,4 for SHA-1 and 1,6 for RIPEMND-160. The proposed system is compared with other related works in both software and hardware.

Performance and energy consumption improvements in microprocessor systems utilizing a coprocessor data-path

The speedups and the energy reductions achieved in a generic single-chip microprocessor system by employing a high-performance data-path are presented. The data-path acts as a coprocessor that accelerates computational intensive kernel sections thereby increasing the overall performance. The authors have previously introduced the data-path which is composed by flexible computational components (FCCs). These components can realize any two-level sequence of primitive operations. The automated coprocessor synthesis method from high-level software description and its integration to a design flow for executing applications on the system is presented. The overall application speedups of eleven real-life applications, relative to the software execution on the microprocessor, are estimated using the design flow. These speedups are close to theoretical bounds and range from 1.78 to 5.84, having an average value of 3.04, while the overhead in circuit area is small. The energy savings range from 41 to 74%, while the reduction in the application energy-delay product has an average value of 80%. A comparison with another high-performance data-path showed that the proposed coprocessor achieves better performance, consumes less energy and has smaller area–time products for the generated data-paths. Additionally, the FCC data-path achieves better performance in accelerating kernels relative to a VLIW DSP core.

Speedups in embedded systems with a high-performance coprocessor datapath

This article presents the speedups achieved in a generic single-chip microprocessor system by employing a high-performance datapath. The datapath acts as a coprocessor that accelerates computational-intensive kernel sections thereby increasing the overall performance. We have previously introduced the datapath which is composed of Flexible Computational Components (FCCs). These components can realize any two-level template of primitive operations. The automated coprocessor synthesis method from high-level software description and its integration to a design flow for executing applications on the system is presented. For evaluating the effectiveness of our coprocessor approach, analytical study in respect to the type of the custom datapath and to the microprocessor architecture is performed. The overall application speedups of several real-life applications relative to the software execution on the microprocessor are estimated using the design flow. These speedups range from 1.75 to 5.84, with an average value of 3.04, while the overhead in circuit area is small. The design flow achieved the acceleration of the applications near to theoretical speedup bounds. A comparison with another high-performance datapath showed that the proposed coprocessor achieves smaller area-time products by an average of 23% for the generated datapaths. Additionally, the FCC coprocessor achieves better performance in accelerating kernels relative to software-programmable DSP cores.

Performance Improvements in Microprocessor Systems Utilizing a Coprocessor Data-Path

The speedups achieved in a generic microprocessor system by employing a high-performance data-path are presented in this work. The data-path acts as a coprocessor that accelerates computational intensive kernel regions thereby increasing the overall performance. It is composed by flexible computational components (FCCs) that can realize any two-level template of primitive operations. The automated coprocessor synthesis method and its integration to a design flow for executing applications on the system is presented. Analytical exploration in respect to the type of the custom data-path and to the microprocessor architecture is performed. The overall application speedups of eight real-life applications, relative to the software execution on the microprocessor, are estimated using the design flow. These speedups range from 1.75 to 3.95, having an average value of 2.72, while the overhead in circuit area is small. A comparison with another high-performance data-path showed that the proposed coprocessor achieves better performance while having smaller area-time products for the generated data-paths

A Framework for Data Partitioning for C++ Data-Intensive Applications

We present an automated framework that partitions the code and data types for the needs of data management in an object-oriented source code. The goal is to identify the crucial data types from data management perspective and separate these from the rest of the code. In this way, the design complexity is reduced allowing the designer to easily focus on the important parts of the code to perform further refinements and optimizations. To achieve this, static and dynamic analysis is performed on the initial C++ specification code. Based on the analysis results, the data types of the application are characterized as crucial or non-crucial. Continuing, the initial code is rewritten automatically in such a way that the crucial data types and the code portions that manipulate them are separated from the rest of the code. Experiments on well-known multimedia and telecom applications demonstrate the correctness of the performed automated analysis and code rewriting as well as the applicability of the introduced framework in terms of execution time and memory requirements. Comparisons with Rational’s QuantifyTM suite show the failure of QuantifyTM to analyze correctly the initial code for the needs of data management.

Power aware data type refinement on the HIPERLAN/2

A power aware data type refinement performed on the data link control layer of the HIPERLAN 2 protocol is presented. Applying static and dynamic analysis on the initial specification code, the crucial data types in terms of memory access and storage are identified. Then proper data structures are selected and an efficient memory architecture is derived, meeting the time constraints and reducing the energy of the system memories. Experimental results show a reduction of the memory energy consumption up to 37% compared with the energy consumption of the memory architecture imposed by the initial specification code.

Improving Performance of Embedded Processors with a High-Performance Coarse-Grained Reconfigurable Data-Path

An embedded system that extends microprocessor cores with a high-performance coarse-grained reconfigurable data-path is introduced. The data-path is composed by computational resources able to realize complex operations which aid in improving the performance of time critical application parts, called kernels. A compilation flow is defined for mapping high-level software descriptions to the microprocessor system. The kernel code is mapped using a properly developed mapping algorithm for the reconfigurable data-path. Extensive exploration is performed by mapping four real-life applications on three different instances of the system. Important overall application speedups have been reported that range from 1.70 to 3.68 relative to an all-processor execution