Gregory F. Pfister

The Yorktown Simulation Engine: Introduction

The Yorktown Simulation Engine (YSE) is a special-purpose, highly-parallel programmable machine for the gate-level simulation of logic. It can simulate up to one million gates at a speed of over two billion gate simulations per second; it is estimated that the IBM 3081 processor could have been simulated on the YSE at a rate of 1000 instructions per second. This is far beyond the capabilities of existing register-level software simulators. The YSE has been designed and is being constructed at the IBM T. J. Watson Research Center. This paper introduces the YSE and describes its top-level architecture.

A single-program-multiple-data computational model for EPEX/FORTRAN

Abstract We present a single-program-multiple-data computational model which we have implemented in the EPEX system to run in parallel mode FORTRAN scientific application programs. The computational model assumes a shared memory organization and is based on the scheme that all processes executing a program in parallel remain in existence for the entire execution; however, the tasks to be executed by each process are determined dynamically during execution by the use of appropriate synchronizing constructs that are imbedded in the program. We have demonstrated the applicability of the model in the parallelization of several applications. We discuss parallelization features of these applications and performance issues such as overhead, speedup, efficiency.

Software Support for the Yorktown Simulation Engine

The Yorktown Simulation Engine (YSE) is a special-purpose, highly-parallel programmable machine for the gate-level simulation of logic. The YSE has been designed and is being constructed at the IBM T. J. Watson Research Center. It can simulate up to one million gates at a speed of over two billion gate simulations per second; it is estimated that the IBM 3081 processor could have been simulated on the YSE at a rate of 1000 instructions per second. This is far beyond the capabilities of existing register-level software simulators. This paper describes the software support for the YSE.

Memory access patterns of parallel scientific programs

A parallel simulator, PSIMUL, has been used to collect information on the memory access patterns and synchronization overheads of several scientific applications. The parallel simulation method we use is very efficient and it allows us to simulate execution of an entire application program, amounting to hundreds of millions of instructions. We present our measurements on the memory access characteristics of these applications; particularly our observations on shared and private data, their frequency of access and locality. We have found that, even though the shared data comprise the largest portion of the data in the application program, on the average a small fraction of the memory references are to shared data. The low averages do not preclude bursts of traffic to shared memory nor does it rule out positive benefits from caching shared data. We also discuss issues of synchronization overheads and their effect on performance.

The IBM Yorktown simulation engine

The IBM Yorktown Simulation Engine (YSE) is a special-purpose, highly parallel programmable machine for the gate-level simulation of logic. A YSE has been constructed at the IBM T. J. Watson Research Center. A full configured YSE could simulate up to two million gates at a speed of over three billion gate simulations per second, it is estimated that a YSE could simulate an IBM 3081 processor, at the gate level, at a rate of 1000 System/370 instructions per second. This paper describes the YSE architecture and software support.

Aspects of the InfiniBand architecture

The InfiniBand Architecture (IBA) is a new industry-standard architecture for server I/O and inter-server communication. It was developed by the InfiniBandSM Trade Association (IBTA) to provide the levels of reliability, availability, performance, and scalability necessary for present and future server systems, levels significantly better than can be achieved with bus-oriented I/O structures. This paper provides a brief description of IBA.

The varieties of single system image

A single system image is the illusion that a collection of otherwise independent computing engines is a single computational resource. But any single system image has a boundary: Within it one perceives unity; outside it there is multiplicity. So many single system images can co-exist in one system. The types of single systems images can be arranged in a hierarchy, ranging from application-level through operating system to hardware. An eight-level hierarchy of single system images is presented and described.

Multipurpose Parallelism for VLSI Cad on the RP3

VLSI CAD application developers need the performance of parallel processing in as general a form as possible. The RP3, which is being developed at IBMs Research Division, provides such generality. Several CAD applications are among the more than 30 applications that have been written in the Epex parallel environment for porting to RP3 when the hardware is complete. Placement by simulated annealing is used here as a significant, deliberately difficult example: its theoretical basis requires serial execution. In the parallel technique used, deviation from the serial algorithm and temporary errors are allowed for more efficient exploitation of parallelism. The result is a convergence rate as good as the original algorithm, with the possibility of efficient execution on hundreds of processors.

Design and implementation of a software simulation engine

Abstract Gate-level logic simulation takes up more CPU time as system complexity increases. A special-purpose system which can cut verification time by several orders of magnitude is described. The Yorktown Simulation Engine (YSE) is a highly parallel programmable machine which can simulate up to 1 M gates at a speed of over 2000M gate simulations per second. It is estimated that the IBM 3081 processor could have been simulated at over 1 000 instructions per second on YSE. Gate-level logic simulation is reviewed and the architecture and hardware implementation of the YSE is described. The software architecture, including compiler, linker and register-level language translator, Ysetran, architecture, are detailed.

Clusters of computers for commercial processing: the invisible architecture

The paper discusses some of the reasons why clusters of computers are successful, particularly in the field of commercial processing. It considers three technical trends: fast performance; fast communications; and distributed programming tool implementation.