Gregory W. Sheets

Electrical backplane equalization using programmable analog zeros and folded active inductors

In this paper, we present a low-power small-area electrical backplane equalizer using programmable analog zeros and folded active inductors. We also present a dc-offset cancellation circuit, which occupies less chip area than the traditional offset cancellation schemes. The equalizer circuit was fabricated in a 1.0-V 90-nm CMOS process. With one zero stage, the equalizer occupies 0.015-mm2 chip area and dissipates 12 mW of power. At 4.25-Gb/s data rate, the equalizer provides 7.8-dB gain boost at the Nyquist frequency. Without the use of any transmitter equalization, the analog zero equalizer demonstrated error-free transmission for pseudorandom-bit-sequence-31 data patterns over 34-in lossy FR4 backplanes.