Guangbing Chen

Modeling of single event pulse with verilog A: Implementation and application

Radiation effects in ICs have been a hot topic in the reliability area for a long time. In the sub-100nm process technology, the Single-Event Effect (SEE) becomes most critical, and the modeling of Single-Event pulse is an important and challenging issue. In this paper a compact model of Single-Event pulse has been developed with VerilogA behavioral language. This model has also been used for the Radiation-Hardened (RH) circuit validation. A VerilogA compact model could link the device level radiation effects to the circuit level simulation and be efficient for the RH circuit design.

Layout design of metal-insulator-metal capacitor array for reducing parasitic influences

In this paper, a layout design of an accurate Metal-insulator-Metal (MIM) capacitor array for reducing parasitic influences is presented. Parasitic capacitance due to interconnecting wires is well-matched. Parasitic resistance can be reduced for less routing track used. Post layout simulation results show that percentage errors of capacitor ratios are generally 0.02% A 16-bit analog-to-digital converter (ADC) including MIM capacitor arrays shows 81dB of SFDR without capacitor mismatch calibration.

Development of a radiation-hardened standard cell library for 65nm CMOS technology

We have developed a radiation-hardened standard cell library for space applications based on the commercial 65nm CMOS technology process. The standard cells are designed using some radiation-hardened (RH) techniques, and the effects of these RH approaches have been validated. Also this 65nm CMOS RH standard cell library has been characterized to support the verilog to GDSII design flow, and the designed radiation tolerant features of this library are: TID > 500 Krad(Si), SEL > 100 MeV·cm2/mg, SEU > 37 MeV cm2/mg.

Development of a radiation-hardened 0.18 µm CMOS standard cell library for space applications

The radiation-hardened standard cell library can greatly improve the life-time and reliability of ASICs used in space applications. In this paper, we have discussed several radiation-hardened techniques, and have used SPICE simulation to validate these approaches. Finally, using these RH techniques, we have developed a radiation-hardened standard cell library based on 0.18 μm CMOS technology.

A radiation-hardened standard cell library for commercial 0.18 µm CMOS technology

The high-performance standard cell library is very important for the ASIC design. A radiation-hardened standard cell library can significantly enhance the reliability and performance of digital circuits that work in a hard radiation environment. We have developed a radiation-hardened standard cell library for the commercial 0.18μm CMOS technology. Some of the radiation-hardened techniques (such as the temporal filtering structure, the P+/N+ guard rings) have been discussed, validated and used for the standard cells. Also we have characterized this RH standard cell library to support the RTL to GDSII ASIC design flow.

Total dose effects on the matching properties of deep submicron MOS transistors

Based on 0.18 μm MOS transistors, for the first time, the total dose effects on the matching properties of deep submicron MOS transistors are studied. The experimental results show that the total dose radiation magnifies the mismatch among identically designed MOS transistors. In our experiments, as the radiation total dose rises to 200 krad, the threshold voltage and drain current mismatch percentages of NMOS transistors increase from 0.55% and 1.4% before radiation to 17.4% and 13.5% after radiation, respectively. PMOS transistors seem to be resistant to radiation damage. For all the range of radiation total dose, the threshold voltage and drain current mismatch percentages of PMOS transistors keep under 0.5% and 2.72%, respectively.