Guanghua Gong

Physics prospects of the Jinping neutrino experiment

Jinping Neutrino Experiment (Jinping) is proposed to significantly improve measurements on solar neutrinos and geoneutrinos in China Jinping Laboratory - a lab with a number of unparalleled features, thickest overburden, lowest reactor neutrino background, etc., which identify it as the world-best low-energy neutrino laboratory. The proposed experiment will have target mass of 4 kilotons of liquid scintillator or water-based liquid scintillator, with a fiducial mass of 2 kilotons for neutrino-electron scattering events and 3 kilotons for inverse-beta interaction events. A number of initial sensitivities studies have been carried out, including on the transition phase for the solar neutrinos oscillation from the vacuum to the matter effect, the discovery of solar neutrinos from the carbon-nitrogen-oxygen (CNO) cycle, the resolution of the high and low metallicity hypotheses, and the unambiguous separation on U and Th cascade decays from the dominant crustal anti-electron neutrinos in China.The China Jinping Underground Laboratory (CJPL), which has the lowest cosmic-ray muon flux and the lowest reactor neutrino flux of any laboratory, is ideal to carry out low-energy neutrino experiments. With two detectors and a total fiducial mass of 2000 tons for solar neutrino physics (equivalently, 3000 tons for geo-neutrino and supernova neutrino physics), the Jinping neutrino experiment will have the potential to identify the neutrinos from the CNO fusion cycles of the Sun, to cover the transition phase for the solar neutrino oscillation from vacuum to matter mixing, and to measure the geo-neutrino flux, including the Th/U ratio. These goals can be fulfilled with mature existing techniques. Efforts on increasing the target mass with multi-modular neutrino detectors and on developing the slow liquid scintillator will increase the Jinping discovery potential in the study of solar neutrinos, geo-neutrinos, supernova neutrinos, and dark matter.

A 20-ps Time-to-Digital Converter (TDC) Implemented in Field-Programmable Gate Array (FPGA) with Automatic Temperature Correction

This paper presents an automatic temperature correction design for carry chain based time-to-digital converter (TDC) in field-programmable gate array (FPGA). The bin-by-bin calibrations under different temperatures are performed for both plain TDC and Wave Union TDC to characterize the influence of temperature variation on the delay time of carry chain. Accordingly, a simplified temperature correction scheme by using a dedicated correction channel to measure the coefficient and correct fine time result for all TDC channels is implemented and tested. This method shows only few picosecond errors for both simulation and measurement. With this correction approach, a TDC precision of 21 ps has been achieved in Cyclone II FPGA under a wide ambient temperature range from 0°C to 60°C. Several design key points are also described in this paper.

Development of a White Rabbit interface for synchronous data acquisition and timing control

Sub-nanosecond precision timing distribution and control are key techniques in various distributed real-time applications, where the proposed White Rabbit (WR) project provides a solution combining both data transmission and timing control via the same media. This paper demonstrates the design and development of a compact, standalone WR node following FPGA Mezzanine Card (FMC) standard, which would work as a common WR interface to different applications. Test results show that the timestamp synchronization precision of 65ps (RMS) has been observed between the node and a WR switch, and the data throughput of over 0.3Gbps has been verified in a preliminary test between the node and a PC host.

Animal SPECT imaging on a shared PET/SPECT ring detector with elliptical-pinhole collimator

In this study, animal SPECT imaging functionality was developed in Nucmed Inliview 3000 PET/SPECT/CT system with an elliptical-pinhole collimator in the shared PET/SPECT ring detector. The collimator was designed to allow simultaneous PET/SPECT dual-tracer imaging. It contains 5 pinhole rings with 10 pinholes per ring. The transverse plane of pinhole was designed to be elliptical to reduce the axial overlap of the SPECT projection. A modified sensitivity formulae for elliptical pinhole was derived and penetration effect was considered in this formulae. Helical SPECT data were acquired by rotating the collimator about the body axis and translating the animal bed along the same axis. Geometrical calibration was implemented to determine the actual parameters of multi-pinhole collimator. OS-EM algorithm was developed and the system matrix was obtained by analytical calculation with the modified sensitivity formulae for elliptical pinhole involved. The penumbra field of elliptical pinhole was defined. Significant artifact reduction was observed after incorporating the penumbra field effect in the reconstruction process. An ultra-micro hot-rod phantom study was performed. The 1.35 mm hot rods can be clearly identified from the reconstructed image. A whole-body mouse bone scan image was presented and shows that the whole skeleton and the vertebra can be clearly seen. A reasonable SPECT/CT fusion image was provided. We conclude that reliable SPECT images can be achieved with this PET/SPECT/CT system with the proposed collimator design and methodology development.

Design of prototyping PMT electronic system for Daya Bay Reactor Neutrino Experiment

This paper describes the design of the PMT Readout VME System developed by IHEP and Tsinghua University for the detector prototype of Daya Bay Reactor Neutrino Experiment. The readout electronics and the trigger event selection, with estimated rates, are presented along with the timing synchronization between all of the electronic elements. The processing of the data from the front-end modules through data storage is discussed, along with the detector control system.

8-channel 14-Bit 125MHz FADC electronics with 1G Ethernet readout based on ZYNQ for HPGe Detector

Traditional High Purity Germanium Detectors need about 14-bit Flash Analog to Digital Convertors to digitalize. For the CJPL in China, a 10Kg HPGe package detectors is developed for dark matter research, every HPGe module is based on 3Kg HPGe detector, totally 40 channels FADC is needed. The 8 channels 125MHz 14bits FADC electronics is designed for analog signal digitalization. The ZYNQ is a new architecture from Xilinx, which include dual ARM Cortex-A9 800MHz 32-Bit processor and some advanced FPGA logic element. In the dual Cortex-A9 processor, the embedded Linux is running with stable and traditional TCP/IP stack, its more easy and ready to use, program by c code, than the other TCP/IP stack based on FPGA logic, and can be easy updated. With the 1000Mbps Ethernet interface, it gives more than 500Mbps Ethernet data throughput without any program tricks. The FPGA logic element can interface the FADC, LTM9011-14 from Linear Tech, with the high speed LVDS interface. Data from FADC can be buffered to the high bandwidth DDR3 SDRAM through the high speed DMA interface with a little CPU intervene. The code in embed Linux based on C program and logic based on VDHL are all combined in one chip with small footprint and lower power consume. Furthermore, we introduce the systems bench mark with more than 500Mbps Ethernet throughput and the ENOB of the FADC.

Development of multi-channel fast SiPM readout electronics for clinical TOF PET detector

Silicon photomultipliers (SiPM) are rapidly adapted in simultaneous time of flight (TOF) PET and MRI imaging system in recent years due to its fast timing response and immunity to magnetic field. The aim of this work is to develop multi-channel fast SiPM readout electronics for clinical TOF PET detector. The detector module is assembled by directly coupling a 12×12 LYSO crystal block to an 8×8 Sensl FB30035 SiPM array. We are developing two approaches of compact readout electronics to handle the large number of SiPM output channels. One is a low noise and high bandwidth, 128-channel ASIC to readout the 64 fast outputs and 64 standard outputs of the 8×8 SiPM array. The other approach is a conventional electronics based multiplexing readout scheme using discrete components. A charge division resistor network reduced 64 channels of standard output to four energy signals, and multiplexing and summing circuits reduced 64 channels of fast output to one timing signal, making the detector block highly compact and scalable. The ASIC design has been finished and its ready for tape-out. Preliminary performance of the detector module readout by conventional electronics was evaluated. 12×12 LYSO crystals were well resolved and identified in the flood image and the average energy resolution was 15.6% ±1.3%. For single crystal pair, 240ps coincidence resolving timing (CRT) was achieved. It was dropped down to 500ps for detector block to single crystal configuration, due to the combination effects of: 1) degradation of fast signal rising edge by output capacitance addition of SiPMs and 2)large white electronic noise and ultrahigh dark count rate. The readout design will be further optimized by increasing the signal bandwidth and reducing noise to get better timing performance at a cost of increasing circuit complexity to a reasonable level. The performance of ASIC readout will be evaluated and good timing performance is expected due to the individual pixel timing pick-off.

A 20-ps temperature compensated Time-to-Digital Converter (TDC) implemented in FPGA

This paper presents a temperature compensation design for carry chain based Time-to-Digital Converter (TDC) in FPGA. The bin-by-bin calibrations under different temperatures are performed for both plain TDC and Wave Union TDC to characterize the influence of temperature variation on the delay time of carry chain which shows all TDC channels have the similar temperature-LUT coefficient. Accordingly, a simplified temperature compensation scheme by using a dedicated correction channel to measure the coefficient and correct fine time result for all TDC channels is implemented and tested. This method shows only few picosecond errors for both simulation and measurement. With this compensation approach, a 21ps RMS TDC resolution has been achieved in Cyclone II FPGA under a wide temperature range from 10°C to 75°C. Several design key points are also described in this paper.

A multi-channel readout electronics system for GEM and MICROMEGAS

A multi-channel readout electronics system for GEM and MICROMEGAS has been developed. It consists of a front-end ASIC, a multi-channel ADC and a FPGA to sample the signal waveforms in real time. The gain of the front-end ASIC can be programmable from 1 mV/fC to 19 mV/fC and the output pulse width can be adjusted from 200 ns to 800 ns. The ENC is measured to be below 2000 e for Cin < 20 pF and below 5000 e for Cin < 60 pF. Detailed circuit performance and test results with detectors will be described in this paper.

The radiation measurement applied to beam lifetime study on the synchrotron radiation facilities

Abstract To collect beam loss information from an accelerator radiation field is helpful to machine study and operation. For a synchrotron radiation storage ring, shower electrons give a distinct clue to loss location and a BLM-XS model detector is suitable to detect them. Recently, we set up a new beam loss monitoring system by this method for National Synchrotron Radiation Laboratory (NSRL) storage ring. It does not interfere with the vacuum chamber and machine operation. Different from other systems, the detectors are used in pairs, fixed on opposite sides of the chamber separately. Some interesting phenomena about beam lifetime were observed. We located exactly where an excessive beam loss took place during ramping process and solved the problem. It was proved that gas accumulated at the front ends of photo-beam lines strongly impacted the electron beam and led to beam lifetime decreases. The cause of beam lifetime decrease because of superconducting wiggler is discussed.