Guangyin Feng

A CMOS W-Band Quasi-Subharmonic Mixer

This letter reports a 4× W-band quasi-subharmonic down-conversion mixer in a 65 nm CMOS technology. Developed from subharmonic mixers, this mixer saves trouble in designing phase-shifters and works well within W-band. Down-conversion is achieved by capturing the phase difference between two sine waves at every half cycle of the local oscillator. The power gain is above 3.5 dB over the entire W-band. The minimum noise figure is 12.5 dB, and the 1 dB compression point is -1.2 dBm.

An 88.5–110 GHz CMOS Low-Noise Amplifier for Millimeter-Wave Imaging Applications

This letter presents a wideband millimeter-wave low-noise amplifier (LNA) in a 65 nm CMOS technology. The amplifier adopts five-stage cascode topology with L-type input matching and T-type output matching. By distributing the peak gains of first four stages at two frequency points, the LNA achieves a flat gain response over a wide bandwidth. The measurement results show that the amplifier features a peak gain of 16.7 dB at 104 GHz, a minimum NF of 7.2 dB, and a 3 dB bandwidth of 21.5 GHz. The LNA consumes 48.6 mW and occupies a compact core area of 0.05 mm2.

Pole-Converging Intrastage Bandwidth Extension Technique for Wideband Amplifiers

To overcome limitations on bandwidth extension in conventional design techniques, a novel pole-converging technique with transformer feedback for intrastage bandwidth extension is proposed and analyzed in this paper. For verification, a three-stage cascode low-noise amplifier (LNA) based on the pole converging and negative drain–source transformer feedback is designed and implemented in a 65-nm CMOS technology. Consuming 27 mW dc power from a 1.8 V supply, the fabricated prototype exhibits peak power gain of 18.5 dB, minimum noise figure of 5.5 dB, 3-dB bandwidth of 30 GHz, and fractional bandwidth of 38.7%. The bandwidth of the three-stage cascode LNA is significantly extended without increasing power consumption and die size.

A 50–59 GHz CMOS Injection Locking Power Amplifier

The injection-locked power amplifier (ILPA) has demonstrated relatively high gain and high efficiency at millimeter-wave frequency. However, their application is still limited by its sensitivity to loading effect and narrow injection locking bandwidth. In this letter, a wide injection locking ILPA using buffered input and output has been proposed and implemented on 65 nm CMOS technology. The buffered input and output can improve the injection locking range and avoid load-to-tank pulling. The measured injection locking range is from 50 GHz to 59 GHz and the peak Power Added Efficiency (PAE) is 16.1% with a maximum output power of 11.39 dBm. Moreover, the die size is merely 260 μm×400 μm excluding pads.

A Compact 57–67 GHz Bidirectional LNAPA in 65-nm CMOS Technology

The letter reports a 57-67 GHz bidirectional low-noise amplifier power amplifier (LNAPA) design. To eliminate the use of T/R switches, the bidirectional matching networks are introduced to connect LNA and PA core circuits in parallel and satisfy the isolation requirements with full consideration of input/output matching of the LNA and PA. Thus, the operation modes are simply selected by gate biasing of the LNA and PA core circuits. Fabricated in a commercial 65-nm CMOS technology, the Rx mode features peak gain of 21.5 dB with gain of > 17 dB over 57-67 GHz, NF of 6.7 dB with PDC of 39.6 mW, while Tx mode achieves peak gain of 24.5 dB with gain of > 17 dB over 57-65 GHz, PSAT of 8.4 dBm, PAE of 8.7% with PDC of 71.1 mW. The reverse isolation in both modes is better than 43 dB. The circuit occupies a compact size of 0.22 mm2.

A 93.4-to-104.8 GHz 57 mW fractional-N cascaded sub-sampling PLL with true in-phase injection-coupled QVCO in 65 nm CMOS

A fully integrated 93.4-to-104.8 GHz 57 mW cascaded PLL, with true in-phase injection-coupled QVCO, occupies 0.88 mm2 in 65 nm CMOS. By cascading the fractional-N PLL and the sub-sampling PLL, good phase noise, high resolution and wide acquisition range are achieved simultaneously. The measured phase noise of QVCO and PLL are -112.67 and -108.75 dBc/Hz at 10 MHz offset, respectively. The FOM and FOMT of the QVCO at 10 MHz offset are -177.5 and -179.0 dBc/Hz, respectively.

A 100-GHz 0.21-K NETD 0.9-mW/pixel Charge-Accumulation Super-Regenerative Receiver in 65-nm CMOS

In this paper, a charge-accumulation technique is proposed in the design of super-regenerative receiver (SRR), which significantly improves the receiver responsivity and sensitivity. Furthermore, a new power-injection method is adopted without loading the

Design of a fully integrated CMOS dual K- and W-band lumped wilkinson power divider

LC

A 65nm CMOS carrier-aggregation transceiver for IEEE 802.11 WLAN applications

- tank of super-regenerative oscillator (SRO). Implemented in a 65-nm CMOS technology with a core area of 0.023 mm2 , the prototype achieves a sensitivity of -67 dBm, a noise-equivalent power (NEP) of 2.8 fW/Hz0.5 , and a noise-equivalent time difference (NETD) of 0.21 K with a power consumption of 0.9 mW.

A 65 nm CMOS LNA for Bolometer Application

A novel design of an on-chip dual-band Wilkinson power divider (DWPD) working at 24 and 77 GHz (K- and W-band) which could be used in the automotive radar system in 65 nm CMOS technology is presented in this paper. The proposed structure is composed of two on-chip inductors and five capacitors. It has the following advantages: (1) constructing a quasi λ/4 transmission line by LC networks, the divider could operate in two frequency bands; (2) as only two inductors are needed in the design, the chip area is remarkably compact, with a die size of only 200 μm × 450 μm, and (3) the structure is symmetrical. Rigorous analysis and equations are given. With the new method, the miniaturized DWPD demonstrates an excellent performance: S11, S22, S23 and S33 are all suppressed down to -15 dB, and the insertion loss is below -1.5 dB at both frequencies.