Guido Torelli

4-Mb MOSFET-selected phase-change memory experimental chip

This paper presents a 4-Mb phase-change memory experimental chip using an MOS transistor as a cell selector. A cascode bit-line biasing scheme allows read and write voltages to be fed to the storage element with adequate accuracy. The chip was integrated with 3-V 0.18-/spl mu/m CMOS technology and experimentally evaluated. A read access time of 45 ns was measured together with a write throughput of 5 MB/s, which represents an improved performance as compared to present NOR Flash memories. Cell current distributions on the 4-Mb array proved chip functionality and a good working window, thus demonstrating the feasibility of a stand-alone phase-change memory with standard CMOS fabrication process.

Nonvolatile multilevel memories for digital applications

When thinking of semiconductor memories, it comes naturally to associate stored bits and memory cells with a one-to-one relationship. That, however, is not really a must nor necessarily the most convenient solution for data storage, since using analog signals and digital-to-analog (D/A) as well as analog-to digital (A/D) conversions a large number of bits could be memorized in a single cell, although, of course, the use of analog signals presents all drawbacks of signal-to-noise ratio that are so well known in electronics. In fact, the real question in this sense concerns the number of bits used for the A/D and D/A conversions, since the conventional (fully) digital case can be seen as the simplest realization of a general approach tending to infinitely precise analog storage (i.e. an infinite number of stored bits per cell) at the other extreme. Naturally, in the real world the conflicting aspects of density (measured in bits per cell) and noise immunity (in a general sense) should be traded off one against the other looking for optimum use of silicon area, of course depending on technology, architectures, circuits and reliability. From this point of view it is obvious that the fully digital approach based on the one-bit one-cell concept does not represent necessarily the best solution. Recently, this general question has assumed real and practical significance for nonvolatile memories, since devices storing two bits per cell are now being introduced on the market. At the same time, in a number of research labs a significant effort is currently being dedicated to the study of the limits and practical convenience of storage density considering the current state of the art in technology and circuit designs. This problem, however, presents a number of interacting aspects concerning cell concept, programming and reading schemes, and architectures and reliability that are of interest well beyond the field of nonvolatile memories, because they are ultimately dealing with the basic question of analog versus digital signals. In this contrast, the present paper considers the question of multilevel nonvolatile memories in all its interacting aspects, analyzing both the current state of the art and the future possibilities.

1-V Rail-to-Rail CMOS OpAmp With Improved Bulk-Driven Input Stage

This paper introduces a CMOS operational amplifier with rail-to-rail input and output voltage ranges, suitable for operation in extremely low-voltage environments. The approach is based on a bulk-driven input stage with extended input common-mode voltage range, in which the effective input transconductance is enhanced by means of a partial positive feedback loop. As a result, a gain and gain-bandwidth product performance similar to that of an amplifier using a gate-driven approach is obtained. Output rail-to-rail operation is achieved by means of a push-pull stage, which is biased in class-AB by using a static feedback loop, thus avoiding frequency limitations inherent in dynamic-feedback tuning schemes. The proposed two-stage operational amplifier was designed to operate with a 1-V supply, and a test chip prototype was fabricated in 0.35-mum standard CMOS technology. The experimental performance features an open-loop DC gain higher than 76 dB and a closed-loop unity-gain bandwidth above 8 MHz when a 1-MOmegapar17-pF load is connected to the amplifier output.

On-chip error correcting techniques for new-generation flash memories

In new-generation flash memories, issues such as disturbs and data retention become more and more critical as a consequence of reduced cell size and decreased oxide thickness. Furthermore, the progressive increase in the cell count within a single die tends to decrease device reliability. In particular, reliability issues turn out to be more critical in multilevel (ML) flash memories, due to the reduced spacing between adjacent programmed levels. It is therefore deemed that the use of on-chip error correction codes (ECCs) will gain widespread acceptance in large-capacity flash memories. ECCs for flash memories must have very fast and compact encoding/decoding circuitry so as to have a minimum impact on memory access time. The area penalty due to check cells must also be minimized. Moreover, specific codes must be developed for ML storage. This paper presents error control coding techniques and schemes for new-generation flash memories, focusing on ML devices. The basic concepts of error control coding are reviewed, and the on-chip ECC design procedure is analyzed. Dedicated codes such as polyvalent ECCs, able to correct data stored in ML memories working at a variable number of bits per cell, and bit-layer organized ECCs are described.

1-V rail-to-rail operational amplifiers in standard CMOS technology

The constraints on the design of CMOS operational amplifiers with rail-to-rail input range for extremely low supply voltage operation, are addressed. Two design approaches for amplifiers based on complementary input differential pairs and a single input pair, respectively, are presented. The first realizes a feedforward action to accommodate the common-mode (CM) component of the input signals to the amplifier input range. The second approach performs a negative feedback action over the input CM signal. Two operational amplifiers based on the proposed approaches have been designed for 1-V total supply operation, and fabricated in a standard 1.2-/spl mu/m CMOS process. Experimental results are provided and the corresponding performances are discussed and compared.

A Multi-Level-Cell Bipolar-Selected Phase-Change Memory

Phase-change memory (PCM) is becoming widely recognized as the most likely candidate to unify the many memory technologies that exist today (Lee, et al., 2007). The combination of non-volatile attributes of flash, RAM-like bit-alterability, and fast reads and writes position PCM to enable changes in the memory subsystems of cellular phones, PCs and countless embedded and consumer electronics applications. This designs multi-level cell (MLC) capabilities combined with long- term scalability reduce PCM costs as only realized before by hard disk drives. MLC technology is challenged with fitting more cell states (4 in the case of 2 bit per cell), along with distribution spreads due to process, design, and environmental variations, within a limited window. We describe a 256Mb MLC test-chip in a 90nm micro-trench (mutrench) PCM technology, and MLC endurance results from an 8Mb 0.18mum PCM test-chip with the same trench cell structure. A program algorithm achieving tightly placed inner states and experimental results illustrating distinct current distributions are presented to demonstrate MLC capability.

Constant-g/sub m/ constant-slew-rate high-bandwidth low-voltage rail-to-rail CMOS input stage for VLSI cell libraries

This paper introduces a general-purpose low-voltage rail-to-rail input stage suitable for analog and mixed-signal applications. The proposed circuit provides, simultaneously, constant small-signal and large-signal behaviors over the entire input common-mode voltage range, while imposing no appreciable constraint for high-frequency operation. In addition, the accuracy of the circuit does not rely on any strict matching of the devices, unlike most of the traditional approaches based on complementary input pairs, which need to compensate for the difference in mobility between electrons and holes with the transistor aspect ratios. Also, the technique is compatible with deep submicrometer CMOS devices, where the familiar voltage-to-current square law in saturation is not completely satisfied. Based on the proposed input stage, a transconductor with rail-to-rail input common-mode range and an input/output rail-to-rail operational amplifier were developed. Both cells were designed to operate with a 3-V single supply and fabricated in standard 0.8-/spl mu/m CMOS technology. Experimental results are provided.

A single-chip optical sensor with analog memory for motion detection

A 64/spl times/64-pixel image sensor with full-frame analog memory and on-chip motion processor is presented. The processor consists of a charge amplifier and an analog subtractor. It uses the switched-capacitor technique and calculates the difference between the values of the signal on each pixel in successive frames. The rate can achieve up to 60 frames/s with limited area and power overhead. The analog memory required for the storage of the previous frame is implemented using implanted capacitors placed within the sensor array. Fabricated in a 1.2-/spl mu/m standard CMOS process with an added metal 3 light-shielding layer, the circuit is fully functional and requires a total core area of 13 mm/sup 2/. >

SET and RESET pulse characterization in BJT-selected phase-change memories

This paper presents program pulse characterization in an 8-Mb BJT-selected phase-change memory test chip. Experimental results of the impact of the bit-line resistance over programming pulse efficiency are provided. Furthermore, in order to compensate for spreads in cell physical parameters in an array portion, a non-conventional staircase-down program pulse is proposed and experimentally evaluated.

A fully symmetrical sense amplifier for non-volatile memories

This paper presents a fully symmetrical sense amplifier topology for advanced non-volatile memories. The proposed structure ensures zero systematic offset, together with adequate rejection of disturbs coming from capacitive coupling with noisy substrate, power supply, and ground. The presented topology has been designed for phase change memories, however, it is also suitable for use in other non-volatile storage devices such as magnetic RAMs and Flash memories. Experimental results on sensing time, offset, and sensitivity demonstrated the effectiveness of the proposed scheme.