Guoda Lian

Practical and Reproducible Mapping of Strains in Si Devices Using Geometric Phase Analysis of Annular Dark-Field Images From Scanning Transmission Electron Microscopy

This letter reports that geometric phase analysis of high-resolution images acquired in the high-angle annular darkfield scanning transmission electron microscopy can map strains at levels of accuracy and reproducibility needed for strained-silicon-device development. Two-dimensional strain maps were reconstructed for a p-type metal-oxide-semiconductor device which was strain-engineered using a recessed source and drain. This metrology provides sufficiently practical and reproducible local-strain tensors which can be measured on a routine basis. The techniques demonstrated here are informative for process development and failure analysis in the semiconductor industry.

Comparison of convergent beam electron diffraction and geometric phase analysis for strain measurement in a strained silicon device

Convergent beam electron diffraction and geometric phase analysis were used to measure strain in the gate channel of a p‐type strained silicon metal–oxide–semiconductor field‐effect transistor. These measurements were made on exactly the same transmission electron microscopy specimen allowing for direct comparison of the relative advantages of each technique. The trends in the strain values show good agreement in both the [] and [001] directions, but the absolute strain values are offset from each other. This difference in the absolute strain measured using the two techniques is attributed to the way the reference strain is defined for each.

Layout Variation Effects in Advanced MOSFETs: STI-Induced Embedded SiGe Strain Relaxation and Dual-Stress-Liner Boundary Proximity Effect

This paper reports two areas of focus for layout variation effects in advanced strained-Si technology: 1) shallow-trench isolation (STI)-induced embedded SiGe (eSiGe) strain relaxation and 2) impact of dual-stress-liner (DSL) boundary on channel mobility. A complete data analysis, including two different strain measurement techniques of nanobeam diffraction and geometric phase analysis, is presented, along with a quantitative understanding for each effect. It is reported that the eSiGe profile can have a significant impact on the STI proximity effect for p-MOSFETs and that DSL boundary proximity can cause significant channel mobility degradation for both n- and p-MOSFETs. Both effects result in the reduction in channel strain along the [110] direction.

Local strain measurement in a strain-engineered complementary metal-oxide-semiconductor device by geometrical phase analysis in the transmission electron microscope

Local strains in the channel and source/drain (S/D) of an advanced complementary metal-oxide-semiconductor device were measured by the geometric phase analysis applied to high resolution transmission electron microscope images. Two-dimensional strain maps were reconstructed for a 45nm p-type metal-oxide-semiconductor device which was strain-engineered using a recessed Si0.82Ge0.18 S/D. Lateral strains were uniform across the channel but vertical strains were found to vary considerably in the channel. Measured strains were used to estimate stresses and hole mobility enhancements.

Strain Profiles in Si Channel of PMOS Devices Affected by Shallow-Trench Isolation Strain Relaxation In Embedded SiGe

Shallow-trench isolation (STI) induced strain in the moat of Si has been studied extensively by using transmission electron microscopy (TEM) based techniques, such as Convergent Beam Electron Diffraction [1] and dark-field electron holography [2]. However the STI proximity effect on the strain in strained Si devices with embedded SiGe (eSiGe) Source/Drain (S/D) has not yet been analyzed. Also the shape of eSiGe S/D is critical to channel strain for advanced technology. In this report, we used NanoBeam Diffraction (NBD) and Geometric Phase Analysis (GPA) to study the channel strain distribution effect by STI proximity, and the shape of eSiGe S/D.

Local Strain Measurement by Geometrical Phase Analysis in the Transmission Electron Microscope Applied to Strain-Engineered CMOS Devices

Extended abstract of a paper presented at Microscopy and Microanalysis 2008 in Albuquerque, New Mexico, USA, August 3 – August 7, 2008