Guoqiang Xing

Demonstration of a 4 Mb, high density ferroelectric memory embedded within a 130 nm, 5 LM Cu/FSG logic process

We demonstrate the bit functionality of a low-voltage, embedded ferroelectric random-access memory constructed using a 130 nm gate and five-level Cu/FSG interconnect process. By inserting the two additional masks required for the eFRAM module into this logic flow, we have co-integrated ferroelectric memory and SRAM on a single wafer.

Hydrogen-Robust Submicron IrOx/Pb(Zr, Ti)O3/Ir Capacitors for Embedded Ferroelectric Memory

We have demonstrated that the scaling of IrOx (Pb(Zr, Ti)O3:PZT)/Ir capacitors can be extended into the submicron regime. The submicron IrOx /PZT/Ir capacitors were fabricated using a one-mask stack-etch process, integrated with an SiO 2 interlayer dielectric, and contacted with Al metallization. The aggregate electrical properties of integrated PZT capacitor arrays are shown to be nearly independent of individual capacitor area in the range between 10 2 µm 2 and 0.12µm 2 . In particular, switched polarization values of more than 30µC/cm 2 were obtained for PZT capacitors with an individual capacitor area of 0.12 µm 2 . This result suggests that the lateral scaling can be achieved down to 0.1 µm 2 . Through the use of appropriate diffusion barriers, hydrogen-robust submicron PZT capacitors are obtained. No degradation in ferroelectric properties of submicron PZT capacitors was observed under the test conditions. These results suggest that PZT capacitors can be integrated into a standard complementary metal oxide semiconductor (CMOS) process flow with minimal degradation.

A novel BST storage capacitor node technology using platinum electrodes for Gbit DRAMs

A new stack capacitor structure using barium strontium titanate (BST) has been developed for Gbit scale DRAMs. The feasibility of fabrication of this structure using Pt as the electrode material is demonstrated through the use of novel processes. An appropriately placed oxidation resistant barrier and adhesion layers enhance the thermal and physical stability of the bottom electrode structure. Electrical results, including AC electrical stress reliability measurements, for 3-D storage nodes with side-wall contribution are presented. Fence-free etching of Pt for bottom electrode formation is shown using a new hardmask based process. Successful back-end integration (ILD and metallization) of BST capacitors is also demonstrated.

Electrical properties of submicron (/spl ges/0.13 /spl mu/m/sup 2/) Ir/PZT/Ir capacitors formed on W plugs

Summary form only given. High-density, embedded ferroelectric memory (FeRAM) has the potential to replace embedded flash, embedded DRAM, and non-cache SRAM and could be a key enabler for future system-on-a-chip applications. Despite this appeal, the evidence that ferroelectric capacitors can be scaled to the submicron regime has been limited. In this paper, we report the fabrication and electrical properties of submicron PZT capacitors formed using both planar bottom electrodes and W plug contact structures. We observe that the aggregate saturation polarization value is nearly independent of individual capacitor area in the measured range from the contact-limited size of 0.12 /spl mu/m/sup 2/ to 10/sup 4/ /spl mu/m/sup 2/. This result suggests that high-density, embedded FeRAM technology may be feasible.

248-nm photolithography compatibility on low-k dielectrics in BEOL interconnects

Printing small geometries using wavelength of 248 nm on low- k materials is not a plug-in photolithography process from one technology to other technology node. In this paper, a method of film characterization of low-k dielectric materials will be discussed. For a characterization of chemical vapor deposited low-k dielectric materials, a positive tone deep UV (DUV) chemically amplified photoresist (CAR) was used as a poisoning gauge. In early development state of low-k dielectrics and copper dual damascene interconnects in back-end-of-line processes, unstable patterning behaviors were observed in spite of using an organic bottom antireflective coating layers on low-k substrates. The initial work was focused on finding the source of lot-to-lot critical dimension (CD) variations and understanding what causes this problem as well. Study indicated a strong correlation that photo CD depended on time interval between photolithography process and previous process step. Significant photo CD shift was introduced by short cycle time from thin film deposition to photolithography process and post via etch clean process to trench photolithography process. To minimize photo CD variations, the process optimizations were necessary in low- k dielectric film deposition, rework, via etch process, and post via etch clean process. As parallel efforts to improve lot-to-lot CD control, various photoresist system, different ambient annealing conditions, various surface organic and inorganic capping techniques were tested. In this experiments, time interval between processes was tightly controlled and maximized the worst case of scenario. Fresh and aged low-k dielectric films were analyzed using time-of- flight secondary ion mass spectrometry and x-ray photoelectron spectroscopy techniques. This work suggested that N2 containing in the film or introducing N2 into low-k dielectric film caused lot-ot-lot photo CD variations.

CD variations from nontrivial mask-related factors

Mask critical dimension (CD) control relies on advanced write tools and resist processes. However, a specified write tool and process does not necessarily guarantee high mask quality. As the mask feature size shrinks to below 500 nm, there are other mask-related factors that can also significantly affect the mask performance. This paper discusses the impact of those non-trivial factors, such as mask writing tool and process control, calibration of mask CD metrology, blank quality of attenuated phase shift mask (ATPSM), pellicle degradation due to 193 nm laser irradiation, and profile of mask features, etc.