Guoqing Jin

A hybrid and adaptive tool-path generation approach of rapid prototyping and manufacturing for biomedical models

In this paper, a hybrid and adaptive tool-path generation approach, which is able to improve geometrical accuracy and build time of rapid prototyping/manufacturing (RP/M) for complex biomedical models, is presented. Firstly, NURBS (Non-Uniform Rational B-Spline)-based curves were introduced to represent the boundary contours of sliced layers to keep the high-fidelity information of original models. Secondly, a hybrid tool-path generation algorithm was then developed to generate contour and zigzag tool-paths. The contour tool-paths are used to fabricate the boundary and neighbouring regions of each sliced layer to preserve geometrical accuracy, and zigzag tool-paths for the internal region of the layer to simplify computing processes and speed up fabrication. Thirdly, based on developed build time and geometrical accuracy analysis models, algorithms were designed to generate an adaptive speed of the RP/Ms nozzle/print head for the contour tool-paths to address the geometrical characteristics of each layer, and to identify the best slope degree of the zigzag tool-paths towards achieving the minimum build time. Finally, five case studies of biomedical models with different geometrical characteristics and complexity were used to verify and demonstrate the improved performance of the approach in terms of processing effectiveness, geometrical accuracy and algorithm robustness.

Sustainable information management for Waste Electrical and Eletronic Equipment

Sustainability has become a critical driving force shaping the future of Waste Electrical and Electronic Equipment (WEEE) management. In this research, lifecycle information and flow management has been investigated to enable transition from the current “management authority-centric reporting model for WEEE” to a new “globally sustainable management model for WEEE”. In order to achieve the target, case studies on LCD TV WEEE have been conducted to understand supply chain information flows and recovery & remanufacturing processes. Based on that, information/flow framework design for WEEE management has been explored.

A systematic selective disassembly approach for Waste Electrical and Electronic Equipment with case study on liquid crystal display televisions

Waste Electrical and Electronic Equipment is one of the major waste streams in terms of quantity and toxicity, and a critical step in Waste Electrical and Electronic Equipment end-of-life processing is through disassembly. Compared with full disassembly, which is a sub-optimal solution due to its high operational cost, selective disassembly is more economic and practical as only selected parts with recycling potential are considered. In this article, a systematic selective disassembly approach for handling Waste Electrical and Electronic Equipment with a maximum disassembly profit in accordance to the Waste Electrical and Electronic Equipment and Restriction of Hazardous Substances Directives has been developed. First, a space interference matrix is generated based on the interference relationship between individual components in the three-dimensional computer-aided design model of Waste Electrical and Electronic Equipment. A matrix analysis algorithm is then applied to obtain all the feasible disassembly sequences through the obtained space interference matrix in a three-dimensional environment. Second, an evaluation and decision-making method is developed to find out an optimal selective disassembly sequence from the obtained feasible disassembly sequences. The evaluation takes into account the disassembly profit and requirements of the Waste Electrical and Electronic Equipment and Restriction of Hazardous Substances Directives, which regulate on recycling rates of different types of products and removal requirements of (1) hazardous, (2) heavy and (3) high-value components. Thus, an optimal solution is a selective disassembly sequence that can achieve the maximum disassembly profit, while complying with the Waste Electrical and Electronic Equipment and Restriction of Hazardous Substances restrictions based on a brute-force search method. Finally, an industrial case on Changhong liquid crystal display televisions of the type LC24F4 is used to demonstrate the effectiveness of the developed approach.

The Current Status of Process Planning for Multi-Material Rapid Prototyping Fabrication

Rapid prototyping (RP) is an innovative manufacturing technology. In recent years, the research to fabricate multi-material products by RP is becoming active. In this paper, we update the recent development of process planning for multi-material RP.

Tool-paths optimization of rapid prototyping to support product verification and collaboration

A slicing algorithm has been developed for directly slicing a CAD (Computer Aided Design) model as RP layers, and based on them closed NURBS (Non-Uniform Rational B-Spline) mathematical curves are introduced to represent the contour of each sliced layer. A tool-path algorithm has been then developed to generate mixed tool-paths with contour offset tool-paths for the boundary of a sliced layer, and zigzag tool-paths for the internal area of the layer. In addition, optimization strategies has been developed to identify the best build degree of zigzag tool-path with the minimum build time and to generate adaptive speeds for contour tool-paths for further reducing the build time. In the end, a human ear model has been used to demonstrate the performance of this research in terms of processing efficiency and surface accuracy.

Energy Consumption Data Based Machine Anomaly Detection

Under some circumstances, the power flux density produced by emissions from a spacecraft suffers the presence of spurious frequencies. This occurs, for example, when idle data with long sequences of zeros are transmitted. At high data rates, randomizers may not be able to solve the problem. Because of the need to comply with the recommendations and standards, this can reflect on severe limits on the maximum data rates achievable. Such problem, experimentally observed in some recent missions, was first studied by Alvarez and Lesthievent, but an effective solution has not been found yet. We discuss the topic and formulate three proposals to compensate the drawback. We show they permit to reduce significantly the required margin at high data rates.Hardened adder and carry logic is widely used in commercial FPGAs to improve the efficiency of arithmetic functions. There are many design choices and complexities associated with such hardening, including circuit design, FPGA architectural choices, and the CAD flow. There has been very little study, however, on these choices and hence we explore a number of possibilities for hard adder design. We also highlight optimizations during front-end elaboration that help ameliorate the restrictions placed on logic synthesis by hardened arithmetic. We show that hard adders and carry chains, when used for simple adders, increase performance by a factor of four or more, but on larger benchmark designs that contain arithmetic, improve overall performance by roughly 15%. We measure an average area increase of 5% for architectures with carry chains but believe that better logic synthesis should reduce this penalty. Interestingly, we show that adding dedicated inter-logic-block carry links or fast carry look-ahead hardened adders result in only minor delay improvements for complete designs.Wideband channelization is a computationally intensive task within software-defined radio (SDR). To support this task, the underlying hardware should provide high performance and allow flexible implementations. Traditional solutions use field-programmable gate arrays (FPGAs) to satisfy these requirements. While FPGAs allow for flexible implementations, realizing a FPGA implementation is a difficult and time-consuming process. On the other hand, multicore processors while more programmable, fail to satisfy performance requirements. Graphics processing units (GPUs) overcome the above limitations. However, traditional GPUs are power-hungry and can consume as much as 350 watts, making them ill-suited for many SDR environments, particularly those that are battery-powered. Here we explore the viability of low-power mobile graphics processors to simultaneously overcome the limitations of performance, flexibility, and power. Via execution profiling and performance analysis, we identify major bottlenecks in mapping the wideband channelization algorithm onto these devices and adopt several optimization techniques to achieve multiplicative speed-up over a multithreaded implementation. Overall, our approach delivers a speedup of up to 43-fold on the discrete AMD Radeon HD 6470M GPU and 27-fold on the integrated AMD Radeon HD 6480G GPU, when compared to a vectorized and multithreaded version running on the AMD A4-3300M CPU.The ever increasing of product development and the scarcity of the energy resources that those manufacturing activities heavily rely on have made it of great significance the study on how to improve the energy efficiency in manufacturing environment. Energy consumption sensing and collection enables the development of effective solutions to higher energy efficiency. Further, it is found that the data on energy consumption of manufacturing machines also contains the information on the conditions of these machines. In this paper, methods of machine anomaly detection based on energy consumption information are developed and applied to cases on our Syil X4 computer numerical control (CNC) milling machine. Further, given massive amount of energy consumption data from large amount machining tasks, the proposed algorithms are being implemented on a Storm and Hadoop based framework aiming at online real-time machine anomaly detection.

Solution space generation for disassembly research on liquid crystal displays televisions

Waste Electrical and Electronic Equipment (WEEE) are one of the most significant waste products in modern societies, and disassembly is a critical step to reduce WEEE. In the past two decades, despite there are many research articles published for disassembly research of WEEE, those researches mainly focus on searching optimised disassembly sequences according to different considerations of stakeholders, while another important problem, i.e., the generation of solution space has received little attentions. However, before applying disassembly planning and optimisation techniques in real industrial cases such as Liquid Crystal Display (LCD) televisions, it cannot evade the issue of the solution space generation. In this paper, an effective approach was developed to generate the solution space for LCD televisions. Firstly, six space interference matrices are generated based on a CAD model, which can be used to represent the space relationship of each components in six directions in a Cartesian coordinate system. A matrix analysis algorithm is then developed to obtain all feasible disassembly sequences by analysing the obtained six space interference matrices in a 3D environment. The result can be used as a solution space to support a disassembly planning method to achieve better economic value and environmental protection requirements within an acceptable runtime. Finally, an industrial case on Changhong LCD television of the type LC24F4 is used to verify and demonstrate the performance of the developed research.