Gurgen Harutyunyan

Fault modeling and test algorithm creation strategy for FinFET-based memories

FinFET transistors are playing an important role in modern technology that is rapidly growing. Embedded memories based on FinFET transistors lead to new defects that can require new embedded test and repair solution. To investigate FinFET-specific faults the existing models and detection techniques are not enough due to a special structure of FinFET transistors. This paper presents a new strategy for investigation of FinFET-specific faults. In addition to fault modeling, a new method is proposed for test algorithm synthesis. The proposed methodology is validated on several real FinFET-based embedded memory technologies. Moreover, new faults are identified that are specific only to FinFETs.

A New Method for March Test Algorithm Generation and Its Application for Fault Detection in RAMs

In this paper, all linked and unlinked static and two-operation dynamic faults are considered. A classification for their description is introduced. To generate a test algorithm for detection of all the considered faults, it was shown that it is not an easy problem. For this purpose, a new structure-oriented method is developed. Based on the proposed method, an efficient test algorithm March LSD of complexity 75N is generated for the detection of the considered linked static and dynamic faults.

Generic BIST architecture for testing of content addressable memories

Minimal March test algorithms are developed for single-port binary and ternary content addressable memories (CAMs). Based on these test algorithms a built-in-self-test (BIST) architecture for testing of CAMs is proposed. It is an extension of an existing BIST architecture for testing of static random access memories (SRAMs) and read-only memories (ROMs). This generic BIST architecture additionally supports the following important CAM specific features: power buffer-zones, multicycle compare operations, half/quarter words and walking patterns.

A Robust Solution for Embedded Memory Test and Repair

This paper presents a robust solution for test and repair of embedded memories. The STAR (Self-Test and Repair) Memory System solution is developed within Synopsys Design Ware allowing users to create, integrate and verify embedded memory test and repair IP in system on chips. The key components and features of the SMS are discussed.

Symmetry Measure for Memory Test and Its Application in BIST Optimization

Programmable Built-in Self-Test (BIST) has been widely used for testing embedded memories. The main disadvantage of having programmability on BIST circuits is the size of Test Algorithm Register (TAR) that becomes very crucial in case of complex test algorithms. To optimize Programmable BIST hardware symmetric March tests are usually used in BIST engines. On the other hand, the used definitions do not reflect completely the existing symmetry in test algorithms and they also do not reflect the fact that the level of symmetry in a given test algorithm can be measured. A new method of symmetry measurement for memory test algorithms and a corresponding metric are introduced. A dependency between symmetry measure and BIST optimization range is analyzed. Optimization experiments that have been done for a number of well-known test algorithms show that the BIST hardware gain could reach 48%. However, the time overhead is negligible in comparison with the hardware gain. The experiments also show that starting from some point a monotone dependency between symmetry measure and BIST hardware area exists.

An effective solution for building memory BIST infrastructure based on fault periodicity

This paper introduces a new solution for building memory BIST infrastructure, based on rules of fault periodicity and regularity in test algorithms. It is proposed to describe all the periodicity and regularity rules in a form of a special Fault Periodicity Table (FPT) and March Test Template (MTT). FPT allows considering any large number of faults in one table and MTT allows obtaining March tests without using special tools for their generation.

Overview study on fault modeling and test methodology development for FinFET-based memories

Rapidly developing FinFET technology, alternative to the conventional planar technology, plays an important role in routing modern silicon industry. Due to unique structure of FinFET transistors the defect types and resulting fault models is different for FinFET transistors compared to planar ones. As a result the well-established flow used for embedded test and repair solutions development for MOSFET-based memories fails to be smoothly deployed for FinFET-based memories as well. Thus there is a need to modify the existing solution to support FinFET-based memories. In the scope of this paper the upgraded test methodology flow is introduced for FinFET-based memories, as well as the high-level overview of the comprehensive study is presented which was conducted using the described flow.

Integrating embedded test infrastructure in SRAM cores to detect aging

One of the most important phenomena degrading Nano-scale Static Random Access Memory (SRAM) reliability is related to Negative-Bias Temperature Instability (NBTI). This paper presents the integration of the OCAS (On-Chip Aging Sensor) approach in the design methodology of 28nm single-port SRAM cores. The goal is to enhance the current test and repair on-chip infrastructure to detect SRAM aging during system lifetime. OCAS is able to detect the aging state of a cell in the SRAM array. The strategy is based on the connection of one OCAS per SRAM column, which periodically performs off-line testing by monitoring write operations into the SRAM cells to detect aging. The approach is application-transparent since it is does not change the SRAM content after testing. SPICE simulations allowed us to analyze the OCAS sensitivity to detect early aging states in this very deep submicron technology, as well as the area, power and performance penalties due to the sensor insertion.

Extending fault periodicity table for testing faults in memories under 20nm

A new solution for building memory BIST infrastructure, based on rules of fault periodicity and regularity in test algorithms was introduced recently. These rules are represented in a form of a Fault Periodicity Table (FPT) considering both known and unknown memory faults in one table. Each column of FPT corresponds to a fault nature which can be associated with a variety of different test mechanisms while each row of FPT corresponds to a fault family determined by the complexity of fault sensitization. In this paper, application of the proposed methodology for description of memory faults in technologies below 20nm, including 16/14nm FinFET-based memories, is shown. Specifically, it is shown that all recently discovered FinFET-specific faults successfully fit into FPT.

Experimental study on Hamming and Hsiao codes in the context of embedded applications

Increasing soft error rate and decreasing technological nodes sizes pave a way for Error Correcting Codes (ECC) widespread use in embedded systems. Depending on application safety goals and acceptable performance and area overhead, different codes can be selected. The goal of this paper is to investigate the efficiency and expediency of two of the most prominent ECC codes, Hamming and Hsiao, in the context of embedded memories and provide practical guidance for their exploitation.