Gustavo Ramos

Modeling, design and demonstration of low-temperature, low-pressure and high-throughput thermocompression bonding of copper interconnections without solders

High-throughput assembly technologies to form Copper (Cu) interconnections without solders at below 200°C, and pitch below 40μm has been a major challenge in the semiconductor industry. A unique solution has been demonstrated by Georgia Institute of Technology to overcome this grand challenge. This technology utilizes thermocompression bonding to form copper interconnections with process tolerances to accommodate non-coplanarities of bumps and warpage of the substrate, without solders. The bonding pressure applied for thermocompression was 365MPa, to enable Cu bump collapse by 3μm. As thermocompression bonders are generally force-limited to 400N, such high bonding pressures may hinder scalability of this technology to fine pitches with higher I/O densities. This paper addresses this manufacturability challenge with the novel Electroless Palladium Autocatalytic Gold (EPAG) surface finish instead of the standard Electroless Nickel Immersion Gold (ENIG) or Electroless Nickel Electroless Palladium Immersion Gold (ENEPIG) finish, previously used to prevent Cu oxidation for bonding load reduction down to 120MPa.

Benefits of pure palladium for ENEP and ENEPIG surface finishes

These investigations show that using electroless pure Pd depositions (without co-deposited phosphorus) can enhance the performance of ENEPIG and ENEP surface finishes. In the case of ENEPIG, the use of pure Pd widens the process window for gold wire bonding and, as demonstrated, allows a reduction in the gold thickness, thus enabling an increase in yield on the assembly side as well as a possible cost reduction. With respect to the ENEP surface finish, the elimination of the immersion gold process step clearly results in a simplified process as compared to ENEPIG. In addition to offering the associated cost reduction, the ENEP surface finish enables next generation interconnection techniques, namely copper wire bonding. The presentation at the ESTC International Conference will provide further details, discussion and interpretation of these test results.

Enabling Chip-to-Substrate All-Cu Interconnections: Design of Engineered Bonding Interfaces for Improved Manufacturability and Low-Temperature Bonding

This paper presents the design and implementation of engineered nanoscale bonding interfaces as an effective strategy to improve manufacturability of Cu-Cu bonding to the level where it can, for the first time, be applied to chip-to-substrate (C2S) assembly. All-Cu interconnections are highly sought after to meet the escalating electrical, thermal, and reliability requirements of a wide range of emerging digital and analog systems. Such applications require low-cost processes with bonding temperatures and pressures ideally below 200°C and 20MPa, respectively, far from existing solutions established in wafer-level packaging. GT-PRC and its industry partners address this technology gap through innovative designs of bonding interfaces, introducing: 1) novel ultra-thin surface finish metallurgies applied on Cu bumps and pads to prevent oxidation and achieve low-temperature assembly, 2) low-cost fly-cut planarization technique to lower bonding pressures, and 3) low-modulus nanocopper foam caps to provide tolerance to non-coplanarities, and further reduce bonding temperatures and pressures.

Scaling Cu Pillars to 20um Pitch and Below: Critical Role of Surface Finish and Barrier Layers

High-performance computing has been aggressively driving pitch and performance requirements for off-chip interconnections over the last several decades, pushing solder-based interconnections to their limits. The most leading-edge Cu pillar technology faces many fundamental challenges in scaling to pitches below 30um, in particular with stress management and increased risks of Au embrittlement as solder volume is reduced All-intermetallic interconnections formed by solid-liquid interdiffusion (SLID) bonding have been concurrently explored to extend solders to finer pitches and improve their performance, but face their own set of manufacturability and reliability challenges that have, so far, limited their use to 3D-ICs. This research comprehensively addresses these challenges with innovative interconnection designs and advances in surface finish metallurgies, which allow for precisely controlled and unique interfacial reactions. A two-fold approach is pursued to: 1) extend scalability of conventional Cu pillars by replacing standard ENEPIG with ultra-thin electroless Pd autocatalytic Au (EPAG) surface finish, and, for further pitch scaling and enhanced electrical and thermal performances, 2) enable void-free, manufacturable all-intermetallic joints solely composed of the metastable Cu6Sn5 phase by introduction of diffusion barrier layers. This paper presents the design, demonstration and characterization of such high-performance solder-based interconnections at 20um pitch, highlighting the strategic role of surface finish and diffusion barrier layers for potential further pitch scaling.

Morphology of Low-Temperature All-Copper Interconnects Formed by Dip Transfer

Flip-chip interconnects made entirely from copper are needed to overcome the intrinsic limits of solder-based interconnects and match the demand for increased current densities. To this end, dip-based all-copper interconnects are a promising approach to form electrical interconnects by sintering copper nanoparticles between the copper pillar and pad. However, the remnant porosity of the copper joint formed between the pillar and the pad limits the performance of this technology. Moreover, the applicability of this technology in the printed circuit board (PCB) industry is endangered by thermo-mechanical stresses that arise during the sintering and by the unknown compatibility with standard finishing layers used to prevent the oxidation of the copper. This work reports three main advances in dip-based all-copper interconnect technology. First, a reduction in the porosity level of the copper joint is obtained by application of pressure during the bonding. Second, a decrease of the bonding temperature to 160 °C is achieved. Third, the compatibility of this technology with standard finishing layers is demonstrated.