Guy Martin Tchamgoue

On-the-fly detection of data races in OpenMP programs

OpenMP provides a portable way to achieve high performance and simple compiler directives to transform a sequential program into parallel program. It is important to detect data races in OpenMP programs, because they may lead to unpredictable results from an execution of the programs. To detect data races that occur during an execution of OpenMP programs, the representative on-the-fly technique, Helgrind+, mainly focuses on reducing false positives. Unfortunately, this technique is still imprecise and inefficient, when applied to large OpenMP programs which use a structured fork-join parallelism with a large number of threads. This paper presents a novel approach which efficiently detects apparent data races without false positives in large OpenMP programs. This approach combines an efficient thread labeling to maintain the logical concurrency of thread segments with a precise detection protocol to analyze conflicting accesses to every shared memory location. We implemented this approach on top of the Pin binary instrumentation framework and compared it with Helgrind+. Empirical results using OpenMP benchmarks show that our technique detects apparent data races without false positives contrarily to Helgrind+, while reducing the average runtime overhead to 19% of Helgrind+ with a similar amount of space overhead.

Hierarchical Real-Time Scheduling Framework for Imprecise Computations

Hierarchical scheduling frameworks provide ways for composing large and complex real-time systems from independent sub-systems. In this paper, we consider the imprecise reward-based periodic task model in a compositional scheduling framework. Thus, we introduce the imprecise periodic resource model to characterize the imprecise resource allocations, and the interface model to abstract the imprecise real-time requirements of the component. The schedulability analysis of mandatory parts is analyzed to meet the minimum requirement of tasks. In addition, we provide a scheduling algorithm for guaranteeing a certain amount of reward, which makes it feasible to compose multiple imprecise components efficiently.

On-the-fly healing of race conditions in ARINC-653 flight software

The ARINC-653 standard architecture for flight software specifies an application executive (APEX) which provides an application programming interface and defines a hierarchical framework which provides health management for error detection and recovery. In every partition of the architecture, however, asynchronously concurrent processes or threads may include concurrency bugs such as unintended race conditions which are common and difficult to remove by testing. A race condition toward a shared data, or data race, is a pair of unsynchronized instructions that access a shared variable with at least one write access. Data races threaten the reliability of shared-memory programs seriously and latently, because they result in unintended nondeterministic executions of the programs. To heal data race during executions of ARINC-653 flight software, this paper instruments on-the-fly race detection into the target program and incorporates on-the-fly race healing into the health management of the ARINC-653 architecture. The race detection signals to the health monitor using the corresponding APEX call, if a data race is detected. The health monitor then responds by invoking an aperiodic, user-defined, error handling process that is assigned the highest possible priority. This special process uses an APEX call to identify and then heals the occurrence of race condition as an application error, one of seven error types defined by ARINC-653. This race-healing process allows the target programs to be assured at run-time that the execution result of the healed program could have been in the original program and therefore no new functional bug has been introduced. This paper evaluates efficiencies of the on-the-fly mechanisms to argue that they are practical to be configured under the ARINC-653 partitions.

Dynamic Voltage Scaling for Power-aware Hierarchical Real-Time Scheduling Framework

Recent research on hierarchical real-time scheduling framework has made it feasible to build large and complex real-time systems. A hierarchical real-time scheduling framework decomposes a system into multiple components which are composed of other sub-components. The component schedulability is analyzed based on the periodic resource model, where each component is guaranteed with a certain amount of periodic resource supply per resource period. Although most of researches have focused on efficient scheduling of a components task set, little work has been done on power-aware scheduling in hierarchical real-time scheduling framework, which has become an important issue in many recent real-time embedded applications. In this paper, we define a new problem for power-aware scheduling in hierarchical framework with periodic resource model. We provide optimal task-level and component-level static DVS (Dynamic Voltage Scaling) schemes. A component-level dynamic DVS scheme is also provided in order to reduce more energy at run-time.

Verification of Data Races in Concurrent Interrupt Handlers

Data races are common in interrupt-driven programs and have already led to well-known real-world problems. Unfortunately, existing dynamic tools for reporting data races in interrupt-driven programs are not only unsound, but they also fail to verify the existence of data races in such programs. This paper presents an efficient and scalable on-the-fly technique that precisely detects, without false positives, apparent data races in interrupt-driven programs. The technique combines a tailored lightweight labeling scheme to maintain logical concurrency between the main program and every instance of its interrupt handlers with a precise detection protocol that analyzes conflicting shared memory accesses by storing at most two accesses for each shared variable. We implemented a prototype of this technique, called iRace, on top of the Avrora simulation framework. An empirical evaluation of iRace revealed the presence of data races in some existing TinyOS components and applications with a worst-case slowdown of only about 6 times on average and an increased average memory consumption of only about 20% in comparison with the original program execution. The evaluation also proved that the labeling scheme alone generates an average runtime overhead of only about 0.4x while consuming only about 12% more memory than the original program execution.

Lightweight Labeling Scheme for On-the-fly Race Detection of Signal Handlers

Data races represent one of the most notorious class of bugs in shared-memory parallel programs since they are hard to reproduce and can lead programs into unintended nondeterministic executions. However, data races can also show up in sequential programs that use signals when a signal handler and the sequential program both access without proper synchronization, a shared variable with at least one write-access operation. Unfortunately, existing tools for race detection in such programs produce high time and space overhead that drastically slow down the monitored program. This overhead is partly due to the use of costly and inappropriate timestamps originally designed for threads’ ordering in multithreaded programs. This paper presents a lightweight labeling scheme for efficient on-the-fly race detection in sequential programs that use signal handlers. This scheme generates constant-sized labels for the program and its signal handlers and determines the logical concurrency between instructions accessing the same shared memory. Generating and comparing concurrency information are done in constant time. The efficiency of the technique and its limited footprint on the program execution make the on-the-fly race detection more practical in sequential programs.

Dynamic race detection techniques for interrupt-driven programs

Data races are notorious concurrency bugs that are difficult to be reproduced and may lead programs into unintended nondeterministic executions. Asynchronous interrupts introduce fine-grained parallelism into interrupt-driven programs making them prone to data races and hard to be thoroughly tested and debugged. Unfortunately, only few tools and techniques have been proposed for dynamic data race detection in interrupt-driven programs that are however widely used in embedded systems. This paper surveys the existing dynamic race detection techniques for interrupt-driven programs, analyzes them to circumscribes the problems they face in reporting data races, and finally highlights the challenges that a dynamic race detection for interrupt-driven program needs to overcome.

Compositional power-aware real-time scheduling with discrete frequency levels

Abstract Power consumption remains a hot issue in all areas of computing ranging from embedded systems that rely on batteries to large scale data centers where reducing the power consumption of computing devices directly affects not only the management cost, but also contributes to a greener computing environment. The power-aware real-time scheduling problem has recently been addressed for a compositional framework with periodic task model under the assumption that a processor can continuously vary its operating frequency and voltage. However, in practice, this technique is only suboptimal and still produce the waste of computational resources. This paper introduces new frequency scaling schemes that statically determine optimal processor speeds at system, component, and task levels with the objective of minimizing the total energy consumption of the entire framework. Since real-world processors support only a finite set of operating frequencies, our algorithms also consider only discrete speed levels and guarantee still that each task meets its deadline. We implemented and evaluated the performance of a prototype framework that incorporates our algorithms on top of the RT-Xen hypervisor in order to provide power-aware compositional real-time scheduling framework to virtual machines.

Compositional real-time scheduling framework for periodic reward-based task model

As the size and complexity of embedded software systems increase, compositional real-time scheduling framework is widely accepted as means to build large and complex systems. A compositional real-time scheduling framework proposes to decompose a system into independent subsystems and provides ways to assemble them into a flexible hierarchical real-time scheduling system while guaranteeing the internal real-time requirements of each subsystem. In this paper, we consider the imprecise reward-based periodic task model in compositional scheduling framework. Thus, we introduce the imprecise periodic resource model to characterize the imprecise resource allocations provided by the system to a single component, and the interface model to abstract the imprecise real-time requirements of the component. The schedulability of mandatory parts is also analyzed to meet the minimum requirement of tasks. Finally, we provide a scheduling algorithm to guarantee a certain amount of reward, which makes it feasible to efficiently compose multiple imprecise components.

Runtime verification of LTL on lossy traces

Runtime verification techniques mostly assume the existence of complete execution traces. However, real-world systems often produce lossy traces due to network issues, partial instrumentation, sampling, and logging failures. A few verification techniques have recently emerged to handle systems with incomplete traces. Some of these techniques sacrifice soundness and may produce imprecise verdicts. The others depend on the recovery of lost events for a sound and meaningful verdict. In this paper, we present an offline algorithm that identifies whether an Ltl (Linear Temporal Logic) formula can be soundly monitored in the presence of a transient loss of events in a trace and constructs a monitor accordingly. More, we introduce the concept of monotonicity to express the persistence of the verdicts of a loss-tolerant monitor regardless of the recovery of the lost events. Our evaluation demonstrates the applicability, efficiency and practicality of the technique on common Ltl patterns, but also on traces from Google Clusters and MPlayer.