H.B. Harrison

The annealing behavior of antimony implanted polycrystalline silicon

Dopant redistribution and sheet resistance of polycrystalline silicon films implanted with 100‐keV Sb+ ions to a dose of 1×1015 cm−2 or 3×1015 cm−2 have been investigated as a function of different annealing conditions. The correlation between Sb depth profiles, as measured by Rutherford backscattering, and sheet resistance provides considerable insight into the Sb doping behavior. In particular, low‐temperature (∼600 °C) short‐time (0.5 h) anneals resulted in good dopant activation without redistribution of the implanted Sb, whereas higher‐temperature anneals (≳900 °C) resulted in considerable redistribution. The sheet resistance of the films appeared to be controlled, to a large extent, by dopant segregation at grain boundaries and the fraction of the redistributed Sb within the grains.

Effect of heat treatment on the properties of gallium‐implanted polycrystalline silicon

Polycrystalline silicon films deposited on silicon dioxide were partially amorphized by implantation with 100 keV gallium ions to a dose of 6×1015 cm−2. These films were then subjected to various heat treatments at 580 and 900 °C using conventional furnace or rapid thermal heating techniques. Sudden drops in sheet resistance occurred at lower temperatures with little change upon further heating. However, the high‐temperature annealed specimen shows only an increase in sheet resistance with time. An explanation of these changes is proposed in terms of a liquid phase melting mechanism taking place during the crystallization of the amorphized near‐surface layer. Transmission electron microscopy and Rutherford backscattering observations support this explanation.

Characterisation of BF2+ and B+implanted silicon after rapid thermal annealing

A detailed characterisation of rapid thermally annealed BF2+ and B+ implanted silicon has been carried out using the complementary techniques of in line 4 point probe and Van der Pauw electrical measurements, transmission electron microscopy, Rutherford backscattering/channeling and secondary ion mass spectrometry. Our results after rapid thermal annealing indicate that defect trapping and release of boron strongly influence both the diffusion behaviour and the electrical properties of the samples.

Specific Contact Resistance Measurements on Multilayer Interconnect Structures.

An integral part of very large scale integrated (VLSI) circuits is the multilayer structures for electrical interconnection and insulation. Many conducting materials are used for interconnection including polysilicon, silicon, silicides, polycides and metals. An important point in considering these materials is the interconnection between them and the corresponding characterization of the interface by way of the specific contact resistance, which directly affects the interfacial contact resistance. For a planar ohmic contact formed between a metal and any layer with a much larger sheet resistance (for example single crystal silicon) a technique based on the transmission line model provides a method of characterizing these contacts. However, for planar contacts between layers with comparable sheet resistivities for example polysilicon to single crystal silicon this technique must be modified. In this paper we review the transmission line approach used to obtain the specific contact resistance between such layers and provide initial results of measurements made on the poly to single crystal interface. We also present a series of test structures, currently under fabrication that will provide more detailed experimental data.

Properties of Gallium Implanted Furnace and Rapidly Annealed Polycrystalline Silicon

Polycrystalline silicon films have been amorphized by implantation with 100keV Ga ions of doses 0.3 and 6×10 15 cm −2 . These films were subsequently recrystallized using either a furnace for longer times lower temperature (∼30 mins, 600° C) or rapid thermal processing (RTP) for shorter times higher temperatures ( ≤ 30 sec, 800° C, 900° C) in an endeavour to suppress any long range movement of the Ga during the anneal phase. It is found that for both the furnace and RTP for temperatures ≤ 800°C no significant movement is observed and that the lower temperature anneal for the highest dose produces the highest electrical conductivity. By contrast however, annealing at 900° C, even though the initial conductivity is higher than for any other anneal we observe a significant reduction with time and extremely rapid movement of the dopant species throughout the original poly layer. An initial rationale for this behaviour is proposed in terms of a liquid phase transformation during annealing.

CHAPTER 11 – Contacts and Interconnections on Semiconductors

Publisher Summary This chapter presents the contacts and interconnections on semiconductors. In the manufacture of an integrated circuit, many devices that are electrically isolated from one another are formed into the semiconductor. These devices then require electrical interconnections to complete the integrated circuit. With the extremely demanding constraints expected to be placed upon the technology of integrated circuit fabrication in the future, in which device geometries will be dramatically reduced to achieve larger packaging densities and larger scales of integration, multilayers of closely packaged, fine-dimension interconnections among devices will be necessary. These interconnections are placed across the surface of the semiconductor and are most often insulated from the underlying substrate and from one another by a dielectric. The many requirements of the interconnection materials on semiconductors used in integrated circuits are often conflicting, and in most cases they are technologically very demanding. For example, they must be multilevel compatible and must display excellent adhesion to underlying and overlaying dielectrics.

Low Ohmicity Contacts to Mono- and Polycrystalline Silicon

With the continued rapid development of integrated circuits and the evolution towards higher chip component densities brought about by down–scaling of device dimensions, it is useful to assess the limits of performance of presently known device structures using current fabrication technology. The silicon gate field effect transistor is of obvious importance, since at the present limit of decreasing dimensions these devices are expected to give comparable speed and lower powerdelay products than their bipolar counterparts. The rapid developments in fabrication methods such as increases in wafer dimensions coupled with the reduction in device dimensions has led to a reduction in maximum processing temperatures. In particular, this downward trend is incompatible with the necessity to lower contact resistance given appropriate device down–scaling. In this paper we present techniques using ion implantation and tailored impurity profiles that are compatible with low temperature ohmic contact formation. The application of these techniques to mono- and polycrystalline silicon are presented. Our results suggest that these techniques show considerable promise for semiconductor device applications. As a consequence, a production technology that optimizes the contact resistance to both gate-poly and drain and source regions is being investigated and current results will be presented.