H. Bergauer

The CMS Drift Tube Trigger Track Finder

Muons are among the decay products of many new particles that may be discovered at the CERN Large Hadron Collider. At the first trigger level the identification of muons and the determination of their transverse momenta and location are performed by the Drift Tube Trigger Track Finder in the central region of the CMS (Compact Muon Solenoid) experiment, using track segments detected in the Drift Tube muon chambers. Track finding is performed both in pseudorapidity and azimuth. Track candidates are ranked and sorted, and the best four are delivered to the subsequent stage, the Global Muon Trigger, which combines them with candidates found in the two complementary muon systems of CMS, the Resistive Plate Chambers and the Cathode Strip Chambers. The concept, design, control and simulation software as well as tests and the expected performance of the Drift Tube Trigger Track Finder system are described.

A 1-GHZ FLASH-ADC MODULE FOR THE TAGGING SYSTEM OF THE CP-VIOLATION EXPERIMENT NA48

Abstract An 8-bit 1-GHz Flash-ADC module has been developed for the tagging system of the CP-violation experiment NA48 at CERN. The module contains two independent channels with 500 MHz sampling rate, which can be interleaved to obtain one channel with an effective sampling rate of 1 GHz. Both FADC chips run continuously and data samples are stored for 524 μs in a ringbuffer memory until they are overwritten by new data. During their “lifetime” data can be extracted from the ringbuffer without disturbing the write cycles. The module fits into a VXI-D crate and uses the VME bus. The design, construction, operation and performance of this module are presented.

The upgrade of the CMS Global Trigger

The Global Trigger is the final step of the CMS Level-1 Trigger. Previously implemented in VME, it has been redesigned and completely rebuilt in MicroTCA technology, using the Virtex-7 FPGA chip family. It will allow to implement trigger algorithms close to the final physics selection. The new system is presented, together with performance tests undertaken in parallel operation with the legacy system during the initial months of Run II of the LHC at a beam energy of 13 TeV.

Design and performance of the phase I upgrade of the CMS Global Trigger

The Global Trigger is the final decision stage of the Level-1 Trigger of the CMS Experiment at the LHC. Previously implemented in VME, it has been redesigned and completely rebuilt in MicroTCA technology, using the Virtex-7 FPGA chip family. This allows implementing trigger algorithms close to the final analysis selection, combining different physical objects. The flexible and compact new system is presented, together with performance tests at a proton-proton centre-of-mass energy of 13 TeV. Firmware and software developments for the operation and validation of the Global Trigger will also be discussed.

MicroTCA-based Global Trigger Upgrade project for the CMS experiment at LHC

The electronics of the first Level Global Trigger (GT) of CMS is the last stage of the Level-1 trigger system [1]. At LHC up to 40 million collisions of proton bunches occur every second, resulting in about 800 million proton collisions. The CMS Level-1 Global Trigger [1], a custom designed electronics system based on FPGA technology and the VMEbus system, performs a quick on-line analysis of each collision every 25 ns and decides whether to reject or to accept it for further analysis. The CMS trigger group of the Institute of High Energy Physics in Vienna (HEPHY) is involved in the Level-1 trigger of the CMS experiment at CERN. As part of the Trigger Upgrade, the Level-1 Global Trigger will be redesigned and implemented in MicroTCA based technology, which allows engineers to detect all possible faults on plug-in boards, in the power supply and in the cooling system. The upgraded Global Trigger will be designed to have the same basic categories of functions as the present GT, but will have more algorithms and more possibilities for combining trigger candidates. Additionally, reconfigurability and testability will be supported based on the next system generation.