H Boeve

Technology and materials issues in semiconductor-based magnetoelectronics

There has been an increased interest in the introduction of magnetic thin films into semiconductors. This interest is motivated by the benefit found in using the magnetic thin-film properties (giant or tunnelling magnetoresistance and hysteresis) in magnetic memory (MRAM) products. Furthermore, the use of the electron spin in electronic, spintronic devices requires intimate ferromagnetic/semiconductor combinations. We review the technology and materials aspects of both the MRAM and spintronics fields that highlight the challenges that must be overcome in order to make magnetic (multilayer) films a standard ingredient in future electronics.

Technology assessment for the implementation of magnetoresistive elements with semiconductor components in magnetic random access memory (MRAM) architectures

We describe the DRAM-like approach towards a non-volatile magnetoresistive memory integrating magnetic and semiconductor devices into one cell. The speed at which the magnetic memory signal can be read depends on many factors. An important factor is the magnetic element itself, the size, magnetic characteristics and absolute resistance. Secondly, the design of the read-out electronics is a key issue. A third determining factor is the technology in which the electronics are fabricated. Some features are indicated that are essential in optimizing MRAM in future.

Low-resistance magnetic tunnel junctions by in situ natural oxidation

Spin-dependent tunneling has received much attention in recent years. In this study, low-resistance exchange-biased magnetic tunnel junctions (down to 2 μm2) were fabricated in a self-aligned way. The insulating barrier was achieved by in situ natural oxidation of very thin Al layers (<1.3 nm). The resistance and magnetoresistance of tunnel junctions is studied as a function of the aluminum thickness for different oxidation times, leading to resistance-area products from 0.1 to 5 kΩ μm2, and tunnel magnetoresistance (TMR) ratios up to 20%. The decrease in TMR for the lowest resistance barriers in the data set is explained by the nonuniformity of the initial Al layer, which has been characterized using different methods. In this case, the optimal oxidation state cannot be reached. The barrier oxidation state can be improved by thermal treatment, by which an increase in TMR is observed for temperatures up to 275 °C.

Strongly reduced bias dependence in spin–tunnel junctions obtained by ultraviolet light assisted oxidation

For future implementation of ferromagnetic tunnel junctions, we need a better understanding of the influence of the insulating barrier preparation method on the junction resistance, tunnel magnetoresistance (TMR), and its voltage bias dependence. In this letter, we focus on the bias dependence of junctions (Co–Al2O3–Ni80Fe20) prepared by ultraviolet light assisted in situ oxidation in an O2 ambient. For an initial Al thickness of 1.3 nm, the resistance times area product of the junctions is 60 kΩ μm2, while showing up to 20% TMR at 5 mV bias. The decrease of TMR with bias voltage up to 1 V is remarkably small leading to V1/2, for which half of the low-bias TMR remains, well over 0.6 V.

Electrodeposited spin valves on n-type GaAs

Soft switching, spin-valve Co/Cu heterostructures have been electrodeposited onto n-type (100) GaAs. A symmetric spin-valve configuration is used which incorporates an artificially hard substructure. A magnetoresistance change of up to 5.4% is observed with sensitivities up to 0.55% per Oersted and a saturation field of 100 Oe, the highest sensitivity so far observed in electrodeposited structures. The magnetoresistance measurements show a double switching step which we conclude is due to the free layers having differing coercivities. The Co/GaAs interface induces an in-plane anisotropy in the films which is responsible for these remarkable spin-valve properties.

Area scaling of planar ferromagnetic tunnel junctions: From shadow evaporation to lithographic microfabrication

In order to meet the requirements for applications in magnetoelectronics (e.g., read heads and magnetic random access memory), a processing scheme for micron-scale ferromagnetic tunnel junctions has been developed. A comparative study of junctions defined by shadow evaporation and by lithographic processing was made, where a similar resistance-area product of nearly 1 GΩ μm2 and a high tunnel magnetoresistance of up to 15% at room temperature were observed for Co/Al2O3/Ni80Fe20 junctions patterned by both methods. A bipolar sensor characteristic at zero field was realized by inducing anisotropies in the two ferromagnetic layers that are orthogonal to each other.

Degradation and time dependent breakdown of stressed ferromagnetic tunnel junctions

Ferromagnetic tunnel junctions are very sensitive to degradation and breakdown, due to the ultrathin (∼1 nm) tunnel barrier. When the junction is stressed with a constant current or voltage, a conductance change of the tunnel junction is observed. Sufficiently high stress will lead to breakdown of the junction. As in SiO2 gate oxide reliability studies, the Weibull distribution plot can be obtained from the time to breakdown data. The dependence of the Weibull function on the area and the stress conditions is studied for the Al2O3 barrier of the tunnel junctions. This is the first step of a systematic study of reliability, which is an important issue for the use of tunnel junctions in, e.g., magnetic random access memory applications.

Growth and tunneling spectroscopy study of Fe/(GaAs, AlAs)/Ga1-xMnxAs ferromagnet/semiconductor heterostructures

Abstract Fully expitaxial tunneling structure Fe/Semiconductor/(Ga,Mn)As was grown and investigated. With semi-insulating (Ga,Mn)As as electrode, strong temperature dependent structure was observed in I–V characteristic. The electronic band structure in the contact region is discussed and the result is explained as inelastic tunneling via impurity states.

Integration of spin valves and GaAs diodes in magnetoresistive random access memory cells

A magnetoresistive random access memory, based on a dynamic random access memory-like floor plan, is demonstrated for an array of magnetic memory cells. Each memory cell consists of a giant magnetoresistive spin-valve structure in series with a GaAs diode. Any single bit in the matrix can be addressed using a coincident current scheme, both for write and read operations. The integration of a series diode in the memory cell yields, for this first demonstrator, read signals of approximately 10 mV.

Evaluation of vacuum bonded GaAs/Si spin-valve transistors

In this article a new type of spin-valve transistor, a hybrid GaAs/Si device, is presented. In this device the Si emitter is replaced by a GaAs emitter launcher structure. The integration of the GaAs with the Si was done by means of a room temperature vacuum bonding technique. By using a soft NiFe/Au/Co spin-valve structure as metal base, a 63% change in collector current is obtained at room temperature for a saturation field of 30 Oe. The corresponding in-plane magnetoresistance is only 1%.