H. Castán

A comparative study of the electrical properties of TiO2 films grown by high-pressure reactive sputtering and atomic layer deposition

Oxide–semiconductor interface quality of high-pressure reactive sputtered (HPRS) TiO2 films annealed in O2 at temperatures ranging from 600 to 900 °C, and atomic layer deposited (ALD) TiO2 films grown at 225 or 275 °C from TiCl4 or Ti(OC2H5)4, and annealed at 750 °C in O2, has been studied on silicon substrates. Our attention has been focused on the interfacial state and disordered-induced gap state densities. From our results, HPRS films annealed at 900 °C in oxygen atmosphere exhibit the best characteristics, with Dit density being the lowest value measured in this work (5–6 × 1011 cm−2 eV−1), and undetectable conductance transients within our experimental limits. This result can be due to two contributions: the increase of the SiO2 film thickness and the crystallinity, since in the films annealed at 900 °C rutile is the dominant crystalline phase, as revealed by transmission electron microscopy and infrared spectroscopy. In the case of annealing in the range of 600–800 °C, anatase and rutile phases coexist. Disorder-induced gap state (DIGS) density is greater for 700 °C annealed HPRS films than for 750 °C annealed ALD TiO2 films, whereas 800 °C annealing offers DIGS density values similar to ALD cases. For ALD films, the studies clearly reveal the dependence of trap densities on the chemical route used.

Electrical characteristics of metal-insulator-semiconductor structures with atomic layer deposited Al2O3, HfO2, and nanolaminates on different silicon substrates

In this work, the electrical characteristics of different atomic layer deposited high-permittivity dielectric films (Al2O3, HfO2, and a nanolaminate of them), with a physical thickness of about 10 nm, are evaluated. An extensive capacitance-voltage and current-voltage characterization at room temperature is carried out on metal-insulator-semiconductor structures fabricated on different p-type and n-type silicon substrates and with Al as metal gate. HfO2 layers are found to exhibit the higher dielectric constant, but they suffer from the largest hysteresis and leakage currents and the lowest breakdown voltages. The nanolaminate stacks, with an intermediate dielectric constant, are found to exhibit more similarities to the Al2O3 layers, withstanding the largest voltages of all the studied dielectric films. The electrical degradation of the layers is evaluated by means of consecutive current-voltage ramps and with constant voltage stress experiments. Results on n-type Si, with electron injection from the sub...

Influence of single and double deposition temperatures on the interface quality of atomic layer deposited Al2O3 dielectric thin films on silicon

An electrical characterization of Al2O3 based metal-insulator-semiconductor structures has been carried out by using capacitance-voltage, deep level transient spectroscopy, and conductance-transient (G-t) techniques. Dielectric films were atomic layer deposited (ALD) at temperatures ranging from 300 to 800 °C directly on silicon substrates and on an Al2O3 buffer layer that was grown in the same process by using 15 ALD cycles at 300 °C. As for single growth temperatures, 300 °C leads to the lowest density of states distributed away from the interface to the insulator [disorder-induced gap states (DIGS)], but to the highest interfacial state density (Dit). However, by using 300∕500°C double growth temperatures it is possible to maintain low DIGS values and to improve the interface quality in terms of Dit. The very first ALD cycles define the dielectric properties very near to the dielectric-semiconductor interface, and growing an upper layer at higher ALD temperature produces some annealing of interfacial s...

Electrical Properties of Atomic-Layer-Deposited Thin Gadolinium Oxide High-k Gate Dielectrics

Amorphous or cubic Gd2O3 thin films were grown from tris ( 2,3-dimethyl-2-butoxy)gadolinium( III) , Gd [OC(CH3)(2)CH(CH3)(2))(3)], and H2O precursors at 350 degrees C. As-deposited Gd2O3 films grown on etched (H-terminated) Si(100) exhibited better leakage current-voltage characteristics as well as lower flatband voltage shift than films grown on SiO2/ Si substrates. Interface trap densities were lower in Al/Gd2O3/ hydrofluoric acid (HF)-etched Si samples annealed at rather high temperatures.

The electrical-interface quality of as-grown atomic-layer-deposited disordered HfO2 on p- and n-type silicon

HfO2 thin films were atomic-layer deposited using different-precursor partial pressures and at different growth temperatures on n- and p-type silicon substrates. The effect of processing parameters and film thickness on the electrical quality of the oxide–semiconductor interface was studied. Deep-level-transient spectroscopy and conductance-transient techniques revealed 3–10 × 1011 cm−2 eV−1 interface trap densities, somewhat dependent on the processing conditions. Charge trapping took place mainly between the semiconductor and defects located at energies close to the majority-carrier-semiconductor-band edge.

Influence of interlayer trapping and detrapping mechanisms on the electrical characterization of hafnium oxide/silicon nitride stacks on silicon

Al/HfO2/SiNx:H/n-Si metal-insulator-semiconductor capacitors have been studied by electrical characterization. Films of silicon nitride were directly grown on n-type silicon substrates by electron cyclotron resonance assisted chemical vapor deposition. Silicon nitride thickness was varied from 3 to 6.6 nm. Afterwards, 12 nm thick hafnium oxide films were deposited by the high-pressure sputtering approach. Interface quality was determined by using current-voltage, capacitance-voltage, deep-level transient spectroscopy (DLTS), conductance transients, and flatband voltage transient techniques. Leakage currents followed the Poole–Frenkel emission model in all cases. According to the simultaneous measurement of the high and low frequency capacitance voltage curves, the interface trap density obtained for all the samples is in the 1011 cm−2 eV−1 range. However, a significant increase in this density of about two orders of magnitude was obtained by DLTS for the thinnest silicon nitride interfacial layers. In thi...

Interface quality study of ECR-deposited and rapid thermal annealed silicon nitride Al/SiNx:H/InP and Al/SiNx:H/In0.53Ga0.47As structures by DLTS and conductance transient techniques

Abstract In this article, we study the influences of the rapid thermal annealing temperature and dielectric composition on the electrical characteristics of ECR-deposited silicon nitride SiN x :H–InP and SiN x :H–InGaAs interfaces. C–V , deep level transient spectroscopy (DLTS) and conductance transient analysis have been applied. As for InP cases, DLTS results reveal that rapid thermal annealing application increases interfacial state density. In contrast, transient conductance measurements show that disorder induced gap-state (DIGS) damage density diminishes when RTA is applied. So, we can conclude that RTA treatments take out the insulator damage to the interface. In the InGaAs-n cases, we have observed that DIGS damage evolution with RTA temperature is opposite to the interfacial state density. This behaviour seems to suggest some temperature activated defect exchange between the insulator and the interface. Finally, as for the insulator composition influence on the interface quality of the InGaAs-n samples, DLTS results suggest that the intermediate x values (1.43 and 1.50) provide better interfaces than extreme x values. Conductance transient measurements add complementary information: insulator damage increases when x increases. Hence, x =1.43 seems to be the best choice to improve the overall interface quality.

Conductance transient, capacitance–voltage and deep-level transient spectroscopy characterization of atomic layer deposited hafnium and zirconium oxide thin films

Abstract High-permittivity HfO 2 and ZrO 2 based oxides grown by atomic layer deposition are investigated. Both ZrO 2 and HfO 2 are materials of high chemical stability and may form relatively stable interface with silicon substrate. To amorphize the structure and increase the resistivity of the dielectric layer, the high-permittivity material was mixed with another high band-gap material such as Al 2 O 3 . This work presents experimental results obtained from electrical characterization of metal–insulator–semiconductor structures based on these dielectrics. Capacitance–voltage, deep-level transient spectroscopy and conductance transient analysis have been used to prove the promising performances of these advanced materials to obtain good interface quality in the incoming CMOS technology. Mixtures of nanolayers of zirconium or hafnium oxide and aluminium oxide yield the best behaviour. They show acceptable density levels of disordered-induced gap states in the insulator level and interface state densities similar to those of stoichiometric oxides.

Electrical properties of thin zirconium and hafnium oxide high-k gate dielectrics grown by atomic layer deposition from cyclopentadienyl and ozone precursors

ZrO2 and reference HfO2 films grown by atomic layer deposition from metal cyclopentadienyls and ozone as precursors to thicknesses ranging from 3.6to13.1nm on etched silicon showed electrical characteristics adequate to high-k dielectrics. The best results in terms of low interface state densities were obtained when (CpMe)2ZrMe2 precursor was used, with Cp denoting the cyclopentadienyl group (C5H5), and Me the methyl group (CH3). The ZrO2 films grown from (CpMe)2Zr(OMe)Me possessed nearly an order of magnitude higher trap state densities. Similar dependence on the precursor chemistry was observed upon recording the flatband voltage time transients. The flatband voltage transients, originating from phonon-assisted tunneling between localized states at oxide silicon interface, were the lowest in HfO2 films grown from (CpMe)2Hf(OMe)Me. The leakage current densities were also lower in the HfO2 films, compared to ZrO2. On the other hand, interfacial trap state densities in HfO2 based capacitors remained higher...

Electrical properties of high-pressure reactive sputtered thin hafnium oxide high-k gate dielectrics

Thin films of hafnium oxide have been deposited by the high-pressure reactive sputtering (HPRS) system. In this growth system the deposition pressure is around 1 mbar, three orders of magnitude higher than in the conventional ones, assuring that both reflected and sputtered particles reach the substrate with a low energy. The amorphous or polycrystalline structure is modified by adjusting the ratio of oxygen to argon of the sputtering gas. The electrical characteristics of both polycrystalline and amorphous films are compared. In all cases, the leakage current can be fitted to Poole–Frenkel emission. Amorphous films show the best characteristics in terms of capacitance–voltage behaviour, leakage current and interfacial state density, with conductance and flat-band voltage transients almost negligible.