H. Kawasaki

Low-frequency dispersion of transconductance in GaAs JFETs and MESFETs with an ion-implanted channel layer

An analytical model of low-frequency dispersion of transconductanced in GaAs FETs which have nonuniform profiles of carrier concentration and mobility is reported. The frequency dependence of surface charge density is incorporated into the model as a variation in the source resistance of the FETs. The model explains the low-frequency dispersion of transconductance in GaAs p-n junction FETs (JFETs) and metal-semiconductor FETs (MESFETs), both of which have a channel layer formed by ion implantation. It is suggested that the low-frequency dispersion of transconductance can be attributed to the charge exchange which occurs with the surface states in GaAs FETs. >

10 K gate GaAs JFET sea of gates

The first GaAs 10 K-gate sea of gates has been successfully fabricated using junction FETs (JFETs) with a gate length of 0.5 mu m. A basic cell is designed to comprise both a direct coupled FET logic (DCFL) four-NOR circuit and a source coupled FET logic (SCFL) inverter circuit with an identical enhancement-type JFET. Each input and output level is designed to be compatible with Si emitter-coupled-logic (ECL), CMOS, and transistor-transistor-logic (TTL) levels. Unloaded and loaded DCFL gate delays are 21 and 180 ps/gate with power consumption of 0.4 and 0.5 mW/gate, respectively. The toggle frequency of the T-type flip-flop is 3.9 and 4.4 GHz for DCFL and SCFL, respectively. >

High-speed DCFL circuits with very shallow junction GaAs JFETs

High-speed DCFL (direct-coupled FET logic) circuits implemented with advanced GaAs enhancement-mode J-FETs are discussed. A divide-by-four static frequency divider operates at up to 6 GHz with a power consumption of 20 mW/flip-flop. A high channel concentration of more than 1*10/sup 18/ cm/sup -3/ together with a very shallow junction depth of less than 30 nm for the p/sup +/-gate results in a transconductance as high as 340 mS/mm at a gate length of 0.8 mu m. Open-tube diffusion of Zn using diethylzinc and arsine makes it possible to control a very shallow p/sup +/-layer less than 10 nm thick. The propagation delay time, as measured with a ring oscillator, was 22 ps/gate with a power consumption of 0.42 mW/gate. >

A low-power 128/spl times/1-bit GaAs FIFO for ATM packet switcher

A low-power 128/spl times/1-b GaAs first-in first-out (FIFO) IC using two-phase dynamic FET logic (TDFL) for high-speed ATM switcher has been successfully demonstrated. In order to overcome the difficulty of low power consumption for the ATM switcher using CMOS FIFO while keeping high-speed operation, a higher speed GaAs FIFO using a low-power circuit technique is designed. The ATM switch architecture, when optimized for use with those higher speed FIFOs, can benefit from reduced power and wiring complexity. The advantage of self-latching property as well as its low power dissipation and compact layout of TDFL gates is used in the FIFO. The FIFO, which contains 270 TDFL gates and 1930 static gates, is shown to operate at 200 MHz with power dissipation of 100 mW. The measured maximum and minimum operating frequencies are 420 and 100 MHz, respectively. The possibility of 10/spl times/ smaller power dissipation, and 4/spl times/ smaller system configuration of the ATM switcher using the GaAs FIFO compared with the CMOS case is expected.

Temperature stability of ultrahigh-speed GaAs JFET ICs

Ultrahigh-speed digital integrated circuits (ICs) implemented with GaAs/int JFETs are confirmed to be reliable in a wide variety of temperatures. Divide-by-256/258 dual-modulus prescaler ICs using source-coupled FET logic (SCFL) circuits that can operate up to 9 GHz have temperature coefficients of operating frequency stability and input power sensitivity of -17.2 MHz/degree and +0.12 dBm/degree between -20 and +100 degrees C, respectively. Direct-coupled FET logic (DCFL) circuits were also confirmed to have very small temperature coefficients. The variations of the maximum operating frequency and the input power sensitivity of the DCFL divide-by-4 divider IC are -1.93 MHz/degree and +0.47 dBm/degree, respectively, between -60 and +100 degrees C. The variation in the threshold voltage of the JFET is -0.88 mV/degree which is very small for the temperature stability of GaAs digital ICs. >