H.L.P. Arjuna Madanayake

A Speed-Optimized Systolic Array Processor Architecture for Spatio-Temporal 2-D IIR Broadband Beam Filters

For high-speed plane-wave filtering applications, real-time 2-D spatio-temporal linear-array broadband beam filters are required, operating at temporal frame rates in excess of hundreds of megahertz. The corresponding application specific VLSI circuits must have low critical-path latencies. A novel high-speed systolic array architecture for a first-order 2-D broadband frequency-planar spatio-temporal beam filter is proposed for this purpose and employs a field-programmable gate array (FPGA) circuit where the critical path latency is minimized by timing optimization of inter- and intra-parallel processor pipelines, together with 3-D look-ahead techniques. The method facilitates single-chip VLSI circuit implementations operating at real-time frame rates of several hundred megahertz.

A Systolic Array 2-D IIR Broadband RF Beamformer

A systolic architecture is proposed for the real-time implementation of broadband 2-D IIR beam filters having applications in ultra-wideband (UWB) radio frequency (RF) antenna arrays. Real-time throughputs of one-frame-per-clock-cycle are achieved. A finite-difference time-domain computational electromagnetic model of a typical indoor propagation environment is used to illustrate that the method significantly reduces the bit error rate of the simulated communication system in the presence of multi-user interference, thereby demonstrating the potential application of the architecture in RF communications.

Low-complexity distributed parallel processor for 2D IIR broadband beam plane-wave filters

Real-time systolic-array-based implementations of VLSI two-dimensional (2D) infinite-impulse-response (IIR) frequency-planar beam plane-wave filters have potentially wide applications in the filtering of spatio-temporal RF broadband plane waves based on their directions of arrival (DOAs). Distributed-parallel-processor (DPP) implementations of the systolic arrays allow synchronous sampling of the 2D input signal array, but because of the direct-form structure they have high circuit complexity. To address the high-complexity problem, the differential-form 2D z-domain transfer function is employed here to obtain a novel DPP systolic-array-based filter architecture. Differential operators are obtained by applying elemental predistortion to the passive LR prototype filter network using series-connected negative-resistance elements. The proposed systolic 2D IIR architecture is implemented on a single Xilinx Virtex-4 Xc4v Sx35-10ff668 FPGA chip. Two examples of broadband plane-wave filtering supporting N = 32 and N = 64 sensors are reported. On-chip test results are achieved using stable real-time tests at frame sample frequencies of up to 90MHz as well as stepped hardware cosimulation in conjunction with a parallel-operating MATLAB/Simulink simulation.

A Systolic-Array Architecture for First-Order 3-D IIR Frequency-Planar Filters

A massively parallel systolic-array architecture is proposed for the implementation of real-time VLSI spatio-temporal 3-D IIR frequency-planar filters at a throughput of one-frame-per-clock-cycle (OFPCC). The architecture is based on a differential-form transfer function and is of low circuit complexity compared with the direct-form architecture. A 3-D look-ahead (LA) form of the transfer function is proposed for maximizing the speed of the implementation, which has a nonseparable 3-D transfer function. The systolic array enables real-time implementation of 3-D IIR frequency-planar filters at radio-frequency (RF) frame-rates and is therefore a suitable building block for 3-D IIR digital filters having beam- and cone-shaped passbands as required for smart-antenna-array beam-forming applications involving the broadband spatio-temporal filtering of plane-waves. The fixed-point systolic-array implementation have a throughput of OFPCC and the tested real-time prototype achieves frame (clock) sample frequencies of up to 90 MHz using one Xilinx Virtex-4 sx35-10ff668 FPGA device.

FPGA Prototyping of Spatio-temporal 2D IIR Broadband Beam Plane-wave Filters

We propose a VLSI architecture for the single-chip realization of 2D spatio-temporal IIR digital filters, consisting of a meshed connection of concurrent identical vector-processors. The architecture is highly scalable, has high temporal throughput (80 MHz or more temporal frame samples/second, per sensor), and has excellent local interconnectivity. A single Xilinx Virtex-II xc2v2000 FPGA device circuit implementation is described for a highly selective first-order 2D infinite impulse response (IIR) broadband frequency-planar beam plane-wave filter, operating at a frame sample rate in excess of 80 MHz over a synchronously sampled linear sensor array consisting of 15 sensors and 15 A/D converters

Systolic array processors for 2D IIR spatio-temporal beamforming wave-digital filters (WDFs)

A systolic-array FPGA processor is proposed for implementing 2D IIR frequency-planar-beam wave digital filters (WDFs) to achieve directional enhancement of propagating broadband plane-waves based on their directions of arrival. The architecture is based on a passive LC ladder prototype network and has a high-throughput of one-frameper-clock-cycle. The structural similarity between the 2D WDF, the 2D analog prototype and the proposed implementation leads to a massively-parallel realization. An example is provided of an implementation on a Xilinx Virtex-4 Sx35-10ff668 FPGA.

Circular array based 2D recursive filtering using a spatio-temporal helix transform

A form-preserving 2D z-domain helix transform is proposed for the synthesis of computable practical-BIBO stable 2D recursive filters computed over uniformly-spaced circular input arrays. The helix transform converts non-computable 2D IIR filters into computable and BIBO stable 1D filters in order to facilitate the required 2D IIR filter transfer function in space-time. Further, a novel scanned-array architecture of the proposed 2D helical circular array processors is proposed that is suitable for VLSI implementation

Effects of Quantization in Systolic 2D IIR Beam Filters on UWB Wireless Communications

Ultra-wideband (UWB) wireless beamforming systems may potentially be implemented digitally at multi-gigahertz clock frequencies using low-precision systolic array realizations of two-dimensional (2D) infinite impulse response (IIR) beam plane-wave filters. The finite precision performance of such filters is analyzed in terms of quantization noise. Extensive Monte Carlo simulations are performed using test vectors that are derived from 2D finite-difference time-domain (FDTD) computational electromagnetic models of the UWB channels. The bit error rate (BER) is determined as a function of signal-to-interference ratio (SIR), with and without beamforming, and for various practical combinations of finite internal wordlengths and A/D converter precisions. It is established that 3-bit A/D converters with 3- to 6-bit internal wordlengths are adequate for good performance and that 4-bit A/D converters with 4- to 7-bit internal wordlengths achieve excellent performance.

Single-chip FPGA architecture for 3D IIR broadband spatio-temporal beam plane-wave filters

A highly-directional FPGA-based broadband beam former is proposed using a novel 3D IIR plane-wave digital filter. This filter acquires the 3D spatio-temporal input signals from spatially-rectangular arrays of sensors that are scanned by only one time-multiplexed A/D converter. The proposed architecture employs a novel scanned-array 3D parallel vector-processor (VP), clocked at 80 MHz, and has the potential to achieve real-time broadband plane-wave filtering on a single low-cost integrated circuit at spatial frame-rates of 19 kHz over a 64 by 64 spatial broadband sensor array

High-frequency systolic broadband beamforming using polyphase 3D IIR frequency-planar digital filters with interleaved A/D sampling

A massively-parallel polyphase systolic array processor is proposed for broadband beamforming using a 3D IIR space-time digital frequency-planar filter that is capable of operating at a throughput of M 2D spatial frames every clock cycle, where M is the number of (poly)phases. The method achieves an M-fold increase in throughput relative to previously known architectures, and has the potential to achieve highly-selective broadband radio-frequency (RF) digital beamforming at frame rates that are several times greater than the clock rate of the VLSI system. The practical real-time performance of the processor is demonstrated using a 3×3 section of a systolic array (that is part of a larger systolic N1 × N2 ≈100 × 100 system), consisting of a locally-interconnected matrix of 9 identical fully-pipelined speed-optimized two phase (M=2) parallel processors on a Xilinx Sx35 FPGA device, having a corresponding measured spatial frame-rate of 100 million frames/second, when clocked at 50 MHz.